HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 667
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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17.3.6
SCSCR is a register used to enable/disable transmission/reception by SCIF, serial clock output,
interrupt requests, and to select transmission/reception clock source for the SCIF.
SCSCR can always be read from and written to by the CPU.
Initial value:
Bit
15 to 8
7
R/W:
Bit:
Serial Control Register (SCSCR)
Bit Name
—
TIE
15
R
0
-
14
-
R
0
13
R
0
-
Initial Value
All 0
0
12
R
0
-
11
R
0
-
10
R
0
-
R/W
R
R/W
R
-
9
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transmit Interrupt Enable
Enables or disables transmit-FIFO-data-empty
interrupt (TXI) request generation when serial
transmit data is transferred from SCFTDR to
SCTSR, the number of data bytes in SCFTDR
falls to or below the transmit trigger set number,
and the TDFE flag in SCFSR is set to 1.
TXI interrupt requests can be cleared using the
following methods: Either by reading 1 from the
TDFE flag, writing transmit data exceeding the
transmit trigger set number to SCFTDR and then
clearing the TDFE flag to 0, or by clearing the
TIE bit to 0.
0: Transmit-FIFO-data-empty interrupt (TXI)
1: Transmit-FIFO-data-empty interrupt (TXI)
R
8
0
-
request disabled
request enabled
TIE
R/W
7
0
Rev. 2.00 Feb. 12, 2010 Page 583 of 1330
R/W
RIE
6
0
R/W
TE
5
0
RE
R/W
4
0
REIE
R/W
3
0
REJ09B0554-0200
R
2
0
-
CKE1 CKE0
R/W
1
0
R/W
0
0
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