HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 346
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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Bit
19
18
17
16
15
Rev. 2.00 Feb. 12, 2010 Page 262 of 1330
REJ09B0554-0200
Bit
Name
BREQEN 0
⎯
MEMMPX 0
DMABST 0
HIZMEM
Initial
Value
0
0
R/W
R/W
R
R/W
R/W
R/W
Description
BREQ Enable
Indicates whether off-chip requests can be accepted.
BREQEN is initialized to the off-chip request acceptance
disabled state by a power-on reset.
0: Off-chip requests are not accepted
1: Off-chip requests are accepted
Reserved
This bit is always read as 0. The write value should
always be 0.
Area 1 to 6 MPX Bus Setting
Sets the MPX interface when areas 1 to 6 are specified
as SRAM interface (or burst ROM interface). This bit is
initialized by a power-on reset.
0: SRAM interface (or burst ROM interface) is selected
1: MPX interface is selected when areas 1 to 6 are
DMAC Burst Mode Transfer Priority Setting
Specifies the priority of burst mode transfers by the
DMAC. When OFF, the priority is as follows: bus
released, refresh, DMAC, CPU. When ON, bus release
and refresh operations are not performed until the end of
the DMAC burst mode transfer. This bit is initialized at a
power-on reset.
0: DMAC burst mode transfer priority setting OFF
1: DMAC burst mode transfer priority setting ON
High Impedance (High-Z) Control
Specifies the state of address and other signals (A[25:0],
BS, CSn, RD/WR, CE2A, CE2B) in software standby
mode and the bus-released state.
0: The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B
1: The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B
when areas 1 to 6 are specified as SRAM interface (or
burst ROM interface)
specified as SRAM interface (or burst ROM interface)
signals made to the high-impedance state in software
standby mode and the bus-released state
signals driven in software standby mode and made to
the high-impedance state in the bus-released state
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