HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1121
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Company:
Part Number:
HD6417760BL200AV
Manufacturer:
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Part Number:
HD6417760BL200AV
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28.4.2
A power-on reset can be performed with an SDIR command. Sending an H-UDI reset assert
command and then an H-UDI reset negate command from the H-UDI pin resets the H-UDI (see
figure 28.3). The required time from the H-UDI reset assert command to H-UDI reset negate
command is the same as the time for holding the reset pin low for a power-on reset.
28.4.3
To generate an interrupt using the H-UDI interrupt function, set the appropriate command in SDIR
via the H-UDI. An H-UDI interrupt is a general exception/interrupt operation, resulting in
branching to the VBR address. The H-UDI returns from the interrupt handler with a RTE
instruction. When an H-UDI interrupt occurs, the exception code H'600 is stored in the interrupt
event register (INTEVT). The priority level for the H-UDI interrupt is controlled by bits IPR3 to
IPR0 in IPRC.
Specifying the appropriate command (Update-IR) sets the INTREQ bit to 1 and then asserts an H-
UDI interrupt request signal. Since this signal is not negated until the INTREQ bit is cleared to 0
by software, the interrupt request will not be missed. While SDIR contains an H-UDI interrupt
command, SDINT is connected between the TDI and TDO pins.
Chip internal reset
CPU state
H-UDI pin
H-UDI Reset
H-UDI Interrupt
Normal
H-UDI reset assert
Figure 28.3 H-UDI Reset
H-UDI reset negate
Reset
Rev. 2.00 Feb. 12, 2010 Page 1037 of 1330
Reset processing
REJ09B0554-0200
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