HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 804
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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Note: * These bits are readable/writable bits. If writing 0, these bits are initialized, although writing 1
Rev. 2.00 Feb. 12, 2010 Page 720 of 1330
REJ09B0554-0200
Bit
1
0
is ignored.
Bit Name
SWNO
IDST
Initial Value
1
1
R/W
R
R
Description
Serial Word Number
The number indicates the current word number.
When TRMD = 0 (Receive Mode):
This bit indicates which system word the current
data in SSIRDR is. Regardless whether the data
has been read out from SSIRDR, when the data in
SSIRDR is updated by transfer from the shift
register, this value will change.
When TRMD = 1 (Transmit Mode):
This bit indicates which system word should be
written in SSITDR. When data is copied to the
shift register, regardless whether the data is
written in SSITDR, this value will change.
Indicates that the serial bus activity has ceased.
This bit is cleared if EN = 1 and the Serial Bus is
currently active.
This bit can be set to 1 automatically under the
following conditions.
SSI = Serial bus master transmitter (SWSD = 1
and TRMD = 1):
This bit is set to 1 if the EN bit is cleared and the
current system word is completed. It can also be
set to 1 when the EN bit has been cleared and the
data that has been written to SSITDR is output on
the serial data input/output pin (SSI_SDATA), j.e.,
the serial data of the system word length is output.
SSI = Serial bus master receiver (SWSD = 1 and
TRMD = 0):
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
SSI = Slave transmitter/ receiver (SWSD = 0):
This bit is set to 1 if the EN bit is cleared and the
current system word is completed. To terminate
the transfer, clear SSICR.EN to 0 and continue to
input the WS signal until SSICR.IDST becomes 1.
Note: If the external device stops the serial bus
Idle Mode Status Flag
clock before the current system word is
completed then this bit will never be set.
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