HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 737

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(2) Serial data transmission
Data transmission in smart card mode includes error signal sampling and repetition processing. An
example of transmission processing is shown in figure 18.5.
No
No
No
(2)
Write transmission data to SITDR
Clear TE bit in SISCR to 0
All data transmitted?
Start transmission
Transmission end
Initialization
TEND=1&&
TDRE=1?
TDRE=1?
ERS=0?
ERS=0?
Figure 18.5 Example of Transmission Processing
Yes
Yes
Yes
Yes
Yes
No
No
(1)
Error processing
Error processing
(3)
(4)
(5)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
and initialize the smart card interface.
cleared to 0.
confirmed that the TDRE flag in SISSR is set to 1.
perform the transmission. At this time, the TDRE
flag is automatically cleared to 0. When
transmission of the start bit is begun, the TEND
flag is automatically cleared to 0, and the TDRE
flag is automatically set to 1.
return to (2).
When transmission is ended, clear the TE bit to 0.
Follow the procedure of item 1 in section 18.4.4,
Confirm that the ERS bit (error flag) in SISSR is
Repeat (2) and (3) in the figure until it can be
Write the transmission data to SITDR, and
When performing continuous data transmission,
Rev. 2.00 Feb. 12, 2010 Page 653 of 1330
REJ09B0554-0200