HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 859
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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bit 0 for example, the bit name is CCS and the bit title in read is Current Connect Status, while
that in write is Clear Port Enable.
• Read
Initial value:
Initial value:
Bit
31 to 21
20
19
18
17
R/W:
R/W:
Bit:
Bit:
Bit Name
⎯
PRSC
OCIC
PSSC
PESC
31
15
R
R
0
0
-
-
30
14
-
R
-
R
0
0
29
13
R
R
0
0
-
-
Initial Value R/W
All 0
0
0
0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R
R
R
R
R
26
10
R
R
0
0
-
-
LSDA PPS
25
R
R
-
0
9
0
Description
Reserved
These bits are always read as 0.
Port Reset Status Change
This bit is set to 1 at the end of the 10-ms port reset
signal.
0: Port reset is not complete
1: Port reset is complete
Overcurrent Indicator Change
This bit is valid only if overcurrent conditions are
reported on a per-port basis. This bit is set when
root hub changes the POCI bit.
0: POCI has not changed
1: POCI has changed
Port Suspend Status Change
This bit is set to 1 when the full resume sequence
has been completed. This sequence includes the
20-ms resume pulse, LS EOP, and 3-ms
resychronization delay.
0: Port resume is incomplete, or PRSC bit is set to 1
1: Port resume is complete
Port Enable Status Change
This bit is set to 1 when a hardware event clears the
PES bit to 0. Writing 1 by HCD does not set this bit
to 1.
0: PES has not changed
1: PES has changed
24
R
R
0
8
1
-
23
R
R
0
0
7
-
-
Rev. 2.00 Feb. 12, 2010 Page 775 of 1330
22
R
R
0
6
0
-
-
21
R
R
0
5
0
-
-
PRSC
PRS
20
R
R
0
4
0
OCIC
POCI
19
R
R
0
3
0
REJ09B0554-0200
PSSC
PSS
18
R
R
0
2
0
PESC
PES
17
R
R
0
1
0
CSC
CCS
16
R
R
0
0
0
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