HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 65
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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Figure 11.11 Example of DMA Transfer in Burst Mode.............................................................436
Figure 11.12 Bus Handling with Two DMAC Channels Operating ............................................440
Figure 11.13 Dual Address Mode/Cycle Steal Mode in External Request 2-Channel Mode
Figure 11.14 Dual Address Mode/Cycle Steal Mode in DMABRG Mode External Bus →
Figure 11.15 Dual Address Mode/Cycle Steal Mode in External Request 2-Channel Mode
Figure 11.16 Dual Address Mode/Cycle Steal Mode in DMABRG Mode External Bus →
Figure 11.17 Dual Address Mode/Burst Mode in External Request 2-Channel Mode External
Figure 11.18 Dual Address Mode/Burst Modes in DMABRG Mode External Bus →
Figure 11.19 Dual Address Mode/Burst Mode in External Request 2-Channel Mode
Figure 11.20 Dual Address Mode/Burst Modes in DMABRG Mode External Bus →
Figure 11.21 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode
Figure 11.22 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode
Figure 11.23 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode
Figure 11.24 Single Address Mode/Cycle Steal Mode in DMABRG Mode External Bus →
Figure 11.25 Single Address Mode/Burst Mode in External Request 2-Channel Mode
Figure 11.26 Single Address Mode/Burst Mode in DMABRG Mode External Bus →
Figure 11.27 Single Address Mode/Burst Mode in External Request 2-Channel Mode
Figure 11.28 Single Address Mode/Burst Mode in DMABRG Mode External Bus →
Figure 11.29 Single Address Mode/Burst Mode in External Request 2-Channel Mode
Figure 11.30 Single Address Mode/Burst Mode in DMABRG Mode External Device →
Figure 11.31 Configuration of DMA for HAC/SSI .....................................................................469
Figure 11.32 Example of HAC DMA Transfer Operation Flow .................................................471
External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) ....443
External Bus/DREQ (Level Detection), DACK (Read Cycle)...............................444
External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) .....445
External Bus/DREQ (Edge Detection), DACK (Read Cycle)................................446
Bus → External Device/DREQ (Level Detection), DACK (Read Cycle)..............447
External Bus/ DREQ (Level Detection), DACK (Read Cycle)..............................448
External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) .....449
External Bus/DREQ (Edge Detection), DACK (Read Cycle)................................450
External Bus → External Device/ DREQ (Level Detection)..................................451
External Bus → External Device/ DREQ (Level Detection)..................................452
External Bus → External Device/ DREQ (Edge Detection) ..................................453
External Device/ DREQ (Edge Detection) .............................................................454
External Bus → External Device/ DREQ (Level Detection)..................................455
External Device/ DREQ (Level Detection) ............................................................456
External Bus → External Device/ DREQ (Edge Detection) ..................................457
External Device/ DREQ (Edge Detection) .............................................................458
External Device → External Bus/ DREQ (Level Detection)/32 Byte Block
Transfer (Bus Width: 32 bits, SDRAM: row hit write) ..........................................459
External Bus/ DREQ (Level Detection)/32 Byte Block Transfer
(Bus Width: 32 bits, SDRAM: row hit write).........................................................460
Rev. 2.00 Feb. 12, 2010 Page lxiii of lxxxii
REJ09B0554-0200
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