HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 843

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 12—Vsync Interrupt Select (VINTSEL): Sets the starting point of the LCDC’s Vsync
interrupt.
Bit 12
VINTSEL
0
1
Bit 8—Vsync Interrupt Enable (VINTE): Sets whether or not to enable LCDC’s Vsync
interrupts.
Bit 8
VINTE
0
1
Bit 0—Vsync Interrupt State (VINTS): Indicates the LCDC’s Vsync interrupt handling state.
This bit is set to 1 at the time a Vsync interrupt is generated. During the Vsync interrupt handling
routine, this bit should be cleared by writing 0 to it.
Bit 0
VINTS
0
1
Notes: • Interrupt Handling Flow:
• When Vsync interrupts are enabled, the VINTE bit must be set to 1 before the DON bit
1. An interrupt signal is input to the CPU.
2. The CPU reads from VINTS.
3. If VINTS is set to 1, a Vsync interrupt has occurred, and the Vsync interrupt
4. If VINTS is cleared to 0, no Vsync interrupt has occurred and another processing is
is set to 1, and the VINTE bit must not be cleared to 0.
Description
access
Description
Description
Vsync interrupt has completed
generated Vsync interrupt has completed
Vsync interrupt is generated at starting point of vertical retrace period for memory
Vsync interrupt is generated at starting point of vertical retrace period for LCD display
Vsync interrupts are disabled
Vsync interrupts are enabled
LCDC did not generate a Vsync interrupt or has been informed that the generated
LCDC has generated a Vsync interrupt and has not yet been informed that the
handling is carried out.
carried out.
Rev.6.00 Mar. 27, 2009 Page 785 of 1036
Section 25 LCD Controller
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)