HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 395

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

fill operation in the event of a cache miss, the missed data is read first, then 16-byte boundary data
including the missed data is read in wraparound mode.
Single Read: Figure 12.15 shows the timing when a single address read is performed. As the burst
length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is
output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is
accessed.
CKIO,
CKIO2
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
Figure 12.14 Synchronous DRAM Burst Read Wait Specification Timing
Tr
Trw
Tc1
Tc2
Tc3/Td1 Tc4/Td2
Rev.6.00 Mar. 27, 2009 Page 337 of 1036
Section 12 Bus State Controller (BSC)
Td3
REJ09B0254-0600
Td4
Tpc