HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 665

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20.1.3
Table 20.1 shows pin list of SIOF.
Table 20.1 SIOF Pin List
Name
Clock input pin
Communication clock pin
Frame sync pin
Transmit data pin
Receive data pin
20.1.4
Table 20.2 lists the internal registers of SIOF.
Table 20.2 SIOF Register Configuration
Name
Serial mode register
Clock select register
Transmit data assign register SITDAR
Receive data assign register
Control data assign register
Serial control register
FIFO control register
Status register
Interruption enabling register
Transmit data register
Receive data register
Transmit control register
Receive control register
Note: * Use the address surrounded by parenthesis when the address translation process by MMU
is not applied. Refer to section 20.3.5, Control Data Interface for more details of the control
data.
Terminal
Register Configuration
Symbol
SIMDR
SISCR
SIRDAR
SICDAR
SICTR
SIFCTR
SISTR
SIIER
SITDR
SIRDR
SITCR
SIRCR
Symbol
SIOMCLK
SCK_SIO
SIOFSYNC
TXD_SIO
RXD_SIO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R/W
R
I/O
I
I/O
I/O
O
I
Initial
Value
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'1000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
Rev.6.00 Mar. 27, 2009 Page 607 of 1036
Function
Master clock input
Serial clock (common for transmitting/
receiving)
Frame synchronized signal (common for
transmitting/receiving)
Transmit data
Receive data
H'040000C2 (H'A40000C2)*
H'040000D6 (H'A40000D6)*
Address
H'040000C0 (H'A40000C0)*
H'040000C4 (H'A40000C4)*
H'040000C6 (H'A40000C6)*
H'040000C8 (H'A40000C8)*
H'040000CC (H'A40000CC)* 16
H'040000D0 (H'A40000D0)*
H'040000D4 (H'A40000D4)*
H'040000E0 (H'A40000E0)*
H'040000E4 (H'A40000E4)*
H'040000E8 (H'A40000E8)*
H'040000EC (H'A40000EC)* 32
Section 20 Serial IO (SIOF)
REJ09B0254-0600
Access
Size
16
16
16
16
16
16
16
16
32
32
32