HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 258

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Interrupt Controller (INTC)
Table 7.8
Item
Time for priority
decision and SR mask
bit comparison
Wait time until end of
sequence being
executed by CPU
Time from interrupt
exception handling
(save of SR and PC)
until fetch of first
instruction of
exception handler is
started
Rev.6.00 Mar. 27, 2009 Page 200 of 1036
REJ09B0254-0600
Interrupt Response Time
0.5 × Icyc
+ 0.5 × Bcyc
+ 0.5 × Pcyc
X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc
5 × Icyc
NMI
IRQ
0.5 × Icyc
+ 1 × Bcyc
+ 4.5 × Pcyc *
5 × Icyc
Number of States
4
PINT
0.5 × Icyc
+ 3.5 × Pcyc
5 × Icyc
Peripheral
Modules
0.5 × Icyc
+ 1.5 × Pcyc *
0.5 × Icyc
+ 3 × Pcyc *
5 × Icyc
6
5
Notes
Interrupt exception
handling is kept
waiting until the
executing instruction
ends. If the number of
instruction execution
states is S *
maximum wait time is:
X = S – 1.
However, if BL is set to
1 by instruction
execution or by an
exception, interrupt
exception handling is
deferred until
completion of an
instruction that clears
BL to 0. If the following
instruction masks
interrupt exception
handling, the
processing may be
further deferred.
1
, the