HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 644

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.9
The FIFO control register 2 (SCFCR2) resets the number of data in the transmit and receive FIFO
register 2, sets the number of trigger data, and contains the permit bit for the loop back test. The
SCFCR2 is always read and written by the CPU. It is initialized to H'00 by the reset, the module
standby function, or in the standby mode.
Bits 7 and 6—Trigger of the Number of Receive FIFO Data (RTRG1 and RTRG0): Set the
number of receive data which sets the receive data full (RDF) flag in the serial status register 2
(SCSSR2). These bits set the RDF flag when the number of receive data stored in the receive
FIFO register 2 (SCFRDR2) is increased more than the number of setting triggers listed below.
Bit 7: RTRG1
0
1
Bits 5 and 4—Trigger of the Number of Transmit FIFO Data (TTRG1 and TTRG0): Set the
number of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag
in the serial status register 2 (SCSSR2). These bits set the TDFE flag when the number of
transmit data in the transmit FIFO data register 2 (SCFTDR2) is decreased less than the number of
setting triggers listed below.
Bit 5: TTRG1
0
1
Note: * Initial value. Values in brackets mean the number of empty SCFTDR2 when a flag occurs.
Rev.6.00 Mar. 27, 2009 Page 586 of 1036
REJ09B0254-0600
Initial value:
FIFO Control Register 2 (SCFCR2)
R/W:
Bit:
RTRG1 RTRG0
R/W
7
0
Bit 6: RTRG0
0
1
0
1
Bit 4: TTRG0
0
1
0
1
R/W
6
0
TTRG1
R/W
5
0
TTRG0
R/W
Number of Received Triggers
4
0
1
4
8
14
Number of Transmitted Triggers
8 (8)*
4 (12)
2 (14)
1 (15)
MCE
R/W
3
0
TFRST
R/W
2
0
RFRST
R/W
0
1
(Initial value)
LOOP
R/W
0
0