HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 265

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 31 to 0—Break Address Mask Register A31 to A0 (BAMA31 to BAMA0): Specifies bits
masked in the channel A break address bits specified by BARA (BAA31 to BAA0).
Bits 31 to 0:
BAMAn
0
1
8.2.3
Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the
break conditions of channel A. A power-on reset initializes BBRA to H'0000.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMAC Cycle Select A (CDA1, CDA0): Selects the CPU cycle or
DMAC cycle as the bus cycle of the channel A break condition.
Bit 7: CDA1
0
*
1
Note: * Don’t care
Initial value:
R/W:
Bit:
Break Bus Cycle Register A (BBRA)
15
—
R
0
Description
Break address bit BAAn of channel A is included in the break condition
Break address bit BAAn of channel A is masked and is not included in the break
condition
Bit 6: CDA0
0
1
0
14
—
R
0
13
—
R
0
12
—
R
0
11
Description
Condition comparison is not performed
The break condition is the CPU cycle
The break condition is the DMAC cycle
—
R
0
10
—
R
0
—
R
9
0
—
R
8
0
CDA1 CDA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0
Rev.6.00 Mar. 27, 2009 Page 207 of 1036
R/W
7
0
R/W
6
0
Section 8 User Break Controller
R/W
5
0
R/W
4
0
R/W
3
0
REJ09B0254-0600
R/W
(Initial value)
2
0
(Initial value)
n = 31 to 0
R/W
1
0
R/W
0
0