HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 804

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 24 USB HOST Module
24.2.17 HcPeriodicStart
HcPeriodicStart Register (H'04000440)
The HcPeriodicStart register has a 14-bit programmable value, which determines the earliest time
when the host controller should start to process the periodic list.
Register: HcPeriodicStart
Bits
31–14
13–0
24.2.18 HcLSThreshold
HcLSThreshold Register (H'04000444)
The HcLSIThreshold register includes an 11-bit value that is used by the host controller to
determine whether or not to authorize the transfer of the LS packed 8 bytes in maximum before
EOF. The host controller and host controller driver cannot change this value.
Register: HcLSThreshold
Bits
31–12
11–0
Rev.6.00 Mar. 27, 2009 Page 746 of 1036
REJ09B0254-0600
Reset
0h
0b
Reset
0h
628h
R/W
—
R/W
R/W
—
R/W
Offset: 40–43
Description
Reserved.
PeriodicStart (PS)
This field is cleared after the hardware has reset. Then this field
is set by HCD while the host controller performs initial settings.
The value is roughly calculated as the value of the
HcFmInterval register minus 10%. When the HcFm Remaining
register reaches the specified value, the processing of the
periodic list has a higher priority than the control/bulk
processing. Consequently, the host controller starts to process
the interrupt list after the completion of the current control/bulk
transaction.
Offset: 44–47
Description
Reserved.
LSThreshold (LST)
This field contains a value to be compared with the
FrameRemaining bit prior to the beginning of low-speed
transaction. The transaction is started only when the Frame
Remaining bit value is beyond the value of the list. The value is
calculated by HCD considering the transmission and set-up
overhead.