HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 278

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 User Break Controller
Bits 27 to 0—Branch Source Address (BSA27 to BSA0): These bits store the last fetched
address before branch.
8.2.12
Note: * Undefined
BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the
flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and
also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight
BRDR registers have queue structure and a stored register is shifted every branch.
Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored.
When a branch destination address is fetched, this flag is set to 1. This flag is cleared to 0 in
reading BRDR.
Bit 31: DVF
0
1
Bits 30 to 28—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 27 to 0—Branch Destination Address (BDA27 to BDA0): These bits store the first fetched
address after branch.
Rev.6.00 Mar. 27, 2009 Page 220 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Branch Destination Register (BRDR)
BDA
DVF
31
15
15
R
R
0
*
Description
The value of BRDR register is invalid
The value of BRDR register is valid
BDA
30
14
14
—
R
R
*
*
BDA
29
13
13
—
R
R
*
*
BDA
28
12
12
—
R
R
*
*
BDA
BDA
27
27
11
11
R
R
*
*
BDA
BDA
26
26
10
10
R
R
*
*
BDA
BDA
25
25
R
R
9
*
9
*
BDA
BDA
24
24
R
R
*
8
8
*
BDA
BDA
23
23
R
R
7
*
7
*
BDA
BDA
22
22
R
R
*
6
6
*
BDA
BDA
21
21
R
R
*
5
5
*
BDA
BDA
20
20
R
R
*
4
4
*
BDA
BDA
19
19
R
R
*
3
3
*
BDA
BDA
18
18
R
R
*
2
2
*
BDA
BDA
17
17
R
R
*
1
1
*
BDA
BDA
16
16
R
R
*
0
0
*