HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 394

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Bus State Controller (BSC)
issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number
of cycles from READ and READA command output cycles Tc1 to Tc4 to the first read data latch
cycle, Td1, can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of A2W1
and A2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of
synchronous DRAM CAS latency cycles.
Figure 12.14 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10,
and TPC is set to 1.
The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is
asserted in each of cycles Td1 to Td4 in a synchronous DRAM cycle. When a burst read is
performed, the address is updated each time CAS is asserted. As the unit of burst transfer is 16
bytes, address updating is performed for A3 and A2 only. The order of access is as follows: in a
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CKIO,
CKIO2
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
Figure 12.13 Basic Timing for Synchronous DRAM Burst Read
Tr
Tc1
Tc2/Td1
Tc3/Td2
Tc4/Td3
Td4
Tpc