HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 591

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
4. After the end of serial transmission, the SCK0 pin is held in the high state.
Figure 17.20 shows an example of SCI transmit operation.
that the transmit data register (SCTDR) contains new data and loads this data from the SCTDR
into the transmit shift register (SCTSR).
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to
1, the SCI requests a transmit-data-empty interrupt (TXI) at this time.
If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external
clock source is selected, the SCI outputs data in synchronization with the input clock. Data are
output from the TxD0 pin in order from the LSB (bit 0) to the MSB (bit 7).
data from the SCTDR into the SCTSR, then begins serial transmission of the next frame. If
TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, transmits the MSB, then holds the
transmit data pin (TxD0) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in
the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
Figure 17.20 Sample SCI Transmission Operation in Clocked Synchronous Mode
Synchronization
Serial data
TDRE
TEND
TXI interrupt
clock
generated
request
Transfer direction
with the TXI interrupt
Writes data to TDR
Bit 0
processing routine
LSB
and clears TDRE
bit to 0
Bit 1
1 frame
Section 17 Serial Communication Interface (SCI)
TXI interrupt
generated
MSB
Bit 7
request
Rev.6.00 Mar. 27, 2009 Page 533 of 1036
Bit 0
Bit 1
TEI interrupt
Bit 6
REJ09B0254-0600
generated
request
Bit 7