HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 504

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 15 Timer (TMU)
15.2
15.2.1
TSTR is an 8-bit read/write register that selects starting or stopping of the timer counters (TCNT)
for channels 0 to 2. TSTR is initialized to H'00 by a power-on reset or manual reset. TSTR is not
initialized in standby mode when the on-chip RTC clock (RTCCLK) is selected as the input clock
for the channel. However, only if the peripheral clock (Pφ) is selected for the channels, it is
initialized in standby mode when the multiplying ratio of PLL circuit 1 is modified and when the
MSTP2 bit in STBCR is set to 1.
Bits 7 to 3—Reserved: These bits are always read as 0 and should be written with 0.
Bit 2—Counter Start 2 (STR2): Selects starting or stopping of the timer counter 2 (TCNT2).
Bit 2: STR2
0
1
Bit 1—Counter Start 1 (STR1): starting or stopping of the timer counter 1 (TCNT1).
Bit 1: STR1
0
1
Bit 0—Counter Start 0 (STR0): Selects starting or stopping of the timer counter 0 (TCNT0).
Bit 0: STR0
0
1
Rev.6.00 Mar. 27, 2009 Page 446 of 1036
REJ09B0254-0600
Initial value:
TMU Registers
Timer Start Register (TSTR)
R/W:
Bit:
Description
Halts TCNT2 operation
Starts TCNT2 operation
Description
Halts TCNT1 operation
Starts TCNT1 operation
Description
Halts TCNT0 operation
Starts TCNT0 operation
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
—
R
3
0
STR2
R/W
2
0
STR1
R/W
0
1
(Initial value)
(Initial value)
(Initial value)
STR0
R/W
0
0