HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 176

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Memory Management Unit (MMU)
3.5.3
A TLB invalid exception results when the logical address is compared to a selected TLB entry
address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception
handling includes both hardware and software operations.
Hardware Operations: In a TLB invalid exception, the SH7727 hardware executes a set of
prescribed operations, as follows:
1. The VPN number of the logical address causing the exception is written to the PTEH register.
2. The logical address causing the exception is written to the TEA register.
3. The way number causing the exception is written to RC in MMUCR.
4. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
5. The PC value indicating the address of the instruction in which the exception occurred is
6. The contents of SR at the time of the exception are written into SSR.
7. The mode (MD) bit in SR is set to 1 to place the SH7727 in the privileged mode.
8. The block (BL) bit in SR is set to 1 to mask any further exception requests.
9. The register bank (RB) bit in SR is set to 1.
10. Execution branches to the address obtained by adding the value of the VBR contents and
Software (TLB Invalid Exception Handler) Operations: The software searches the page tables
in external memory and assigns the required page table entry. Upon retrieving the required page
table entry, software must execute the following operations:
1. Write the values of the physical page number (PPN) field and the values of the protection key
2. If using software for way selection for entry replacement, write the desired value to the RC
3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
4. Issue the RTE instruction to terminate the handler and return to the instruction stream. The
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EXPEVT register.
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the delayed branch instruction is written to the SPC.
H'00000100, and the TLB protection violation exception handler starts.
(PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page
table entry recorded in the external memory to the PTEL register.
field in MMUCR.
RTE instruction should be issued after two LDTLB instructions.
TLB Invalid Exception