HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 491

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 1—Reserved: This is a readable/writable bit, but the write value should be always be 0.
Bit 0—Count start 0 (STR0): Selects whether the compare-match timer counter 0 is operated or
halted.
Bit 0: STR0
0
1
Compare-Match Timer Control/Status Register 0 (CMCSR0)
The compare-match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates a
compare-match occurrence and sets the incrementation clock. CMCSR0 is initialized to H'0000 by
a reset, but it retains its previous values in standby mode.
Note: * Only a 0 can be written, to clear the flag.
Bits 15 to 8 and 5 to 2—Reserved: These bits are always read as 0and should only be written
with 0.
Bit 7—Compare-Match Flag (CMF): This flag indicates that a compare-match of the compare-
match timer counter 0 (CMCNT0) and compare-match constant register 0 (CMCOR0) occurred.
Bit 7: CMF
0
1
Bit 6—Reserved: This is a readable/writable bit, but the write value should be always be 0.
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Description
CMCNT0 count operation is halted
CMCNT0 count operation is provided
Description
CMCNT0 and CMCOR0 have not matched
Clear condition: Write 0 to CMF after reading CMF = 1
A compare-match of CMCNT0 and CMCOR0 occurred
R/(W)*
CMF
15
—
R
0
7
0
R/W
14
—
—
R
0
6
0
13
—
—
R
R
0
5
0
Section 14 Direct Memory Access Controller (DMAC)
12
—
—
R
R
0
4
0
Rev.6.00 Mar. 27, 2009 Page 433 of 1036
11
—
—
R
R
0
3
0
10
—
—
R
R
0
2
0
REJ09B0254-0600
CKS1
R/W
—
R
9
0
1
0
(Initial value)
(Initial value)
CKS0
R/W
—
R
8
0
0
0