HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 21
![IC SUPERH MPU ROMLESS 240QFP](/photos/28/62/286203/240-bfqfp__prqp0240kc-b_sml.jpg)
HD6417727F100C
Manufacturer Part Number
HD6417727F100C
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100C
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417727F100C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.6
Section 5 Cache
5.1
5.2
5.3
5.4
5.5
Section 6 X/Y Memory
6.1
6.2
6.3
6.4
Section 7 Interrupt Controller (INTC)
7.1
7.2
4.5.2
4.5.3
Usage Notes ...................................................................................................................... 147
Overview........................................................................................................................... 149
5.1.1
5.1.2
5.1.3
Register Description.......................................................................................................... 151
5.2.1
5.2.2
Cache Operation................................................................................................................ 154
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Memory-Mapped Cache ................................................................................................... 157
5.4.1
5.4.2
Usage Examples................................................................................................................ 160
5.5.1
5.5.2
Overview........................................................................................................................... 161
6.1.1
X/Y Memory Access from the CPU ................................................................................. 162
X/Y Memory Access from the DSP.................................................................................. 164
X/Y Memory Access from the DMAC ............................................................................. 164
Overview........................................................................................................................... 165
7.1.1
7.1.2
7.1.3
7.1.4
Interrupt Sources ............................................................................................................... 169
7.2.1
General Exceptions .............................................................................................. 141
Interrupts.............................................................................................................. 146
Features................................................................................................................ 149
Cache Structure.................................................................................................... 149
Register Configuration......................................................................................... 151
Cache Control Register (CCR) ............................................................................ 151
Cache Control Register 2 (CCR2) ....................................................................... 152
Searching the Cache............................................................................................. 154
Read Access......................................................................................................... 156
Prefetch Operations.............................................................................................. 156
Write Access ........................................................................................................ 156
Write-Back Buffer ............................................................................................... 157
Coherency of Cache and External Memory ......................................................... 157
Address Array ...................................................................................................... 157
Data Array............................................................................................................ 158
Invalidating Specific Entries................................................................................ 160
Reading the Data of a Specific Entry................................................................... 160
Features................................................................................................................ 161
Features................................................................................................................ 165
Block Diagram..................................................................................................... 166
Pin Configuration................................................................................................. 167
Register Configuration......................................................................................... 167
NMI Interrupts ..................................................................................................... 169
.................................................................................................................... 149
...................................................................................................... 161
........................................................................... 165
Rev.6.00 Mar. 27, 2009 Page xix of lvi
REJ09B0254-0600
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