HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 160

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Memory Management Unit (MMU)
address and the page control information are read from the TLB and the physical address is
determined.
If the logical address is not registered in the TLB, a TLB miss exception occurs and processing
will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in
external memory is searched and the corresponding physical address and the page control
information are registered in the TLB. After returning from the handler, the instruction that caused
the TLB miss is re-executed. When the MMU is enabled, address translation information that
results in a physical address space of H'80000000 to H'FFFFFFFF should not be registered in the
TLB.
When the MMU is disabled, the logical address is used directly as the physical address. As the
SH7727 supports a 29-bit address space as the physical address space, the top 3 bits of the
physical address are ignored, and constitute a shadow space (see section 12, Bus State Controller
(BSC)). For example, addresses H'00001000 in the P0 area, H'80001000 in the P1 area,
H'A0001000 in the P2 area, and H'C0001000 in the P3 area are all mapped onto the same physical
address. When access to these addresses is performed with the cache enabled, an address with the
top 3 bits of the physical address masked to 0 is stored in the cache address array to ensure data
congruity.
Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual
memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual
memory mode, multiple processes run in parallel using the logical address space exclusively and
the physical address corresponding to a given logical address is specified uniquely. In multiple
virtual memory mode, multiple processes run in parallel sharing the logical address space, so a
given logical address may be translated into different physical addresses depending on the process.
By the value set to the MMU control register (MMUCR), either single or multiple virtual mode is
selected. In terms of operation, the only difference between single virtual memory mode and
multiple virtual memory mode is in the TLB address comparison method (see section 3.3.3, TLB
Address Comparison).
Address Space Identifier (ASID): In multiple virtual memory mode, the address space identifier
(ASID) is used to differentiate between processes running in parallel and sharing logical address
space. The ASID is 8 bits in length and can be set by software setting of the ASID of the currently
running process in PTEH within the MMU. When the process is switched using the ASID, the
TLB does not have to be purged.
In single virtual memory mode, the ASID is used to provide memory protection for processes
running simultaneously and using the logical address space exclusively (see section 3.4.2, MMU
Software Management).
Rev.6.00 Mar. 27, 2009 Page 102 of 1036
REJ09B0254-0600