HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 602

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch
destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by
a power-on reset. Other bits are not initialized by a power-on reset. The eight BRDR registers have
a queue structure and a stored register is shifted at every branch.
22.2.13 Break ASID Register A (BASRA)
BASRA is an 8-bit readable/writable register that specifies ASID which becomes the break
condition for channel A. BASRA is in CCN.
Rev. 2.00, 09/03, page 554 of 690
Bit
31
30 to
28
27 to 0
Bit
7 to 0
Bit
Name
DVF
BDA27 to
BDA0
Bit
Name
BASA7
to
BASA0
Initial
Value
0
0
Undefined
Initial
Value
R/W
R/W
R/W
R
R
R
Description
BRDR Valid Flag
Indicates whether a branch destination address is
stored. When a branch destination address is
fetched, this flag is set to 1. This flag is cleared to 0
by reading BRDR.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
Reserved
These bits are always read as 0.
Branch Destination Address
Store bits 27 to 0 of the branch destination address.
Description
Break ASID A
Store ASID (bits 7 to 0) which is the break condition
for channel A.