HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 14

MPU 3V 0K PB-FREE 208 FP

HD6417705F133BV

Manufacturer Part Number
HD6417705F133BV
Description
MPU 3V 0K PB-FREE 208 FP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417705F133BV

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
105
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Item
6.1 Features
Figure 6.1 Block Diagram
of INTC
6.4.6 Interrupt Exception
Handling and Priority
Table 6.4 Interrupt
Exception Handling Sources
and Priority (IRQ Mode)
7.4.2 CSn Space Bus
Control Register (CSnBCR)
(n = 0, 2, 3, 4, 5A, 5B, 6A,
6B)
7.4.5 Refresh Timer
Control/Status Register
(RTCSR)
7.4.6 Refresh Timer
Counter (RTCNT)
Rev. 2.00, 09/03, page xii of xlvi
Page
126
140
160
161
177
179
Revisions (See Manual for Details)
CMT deleted
PINT15−PINT0
IPR (bit numbers) amended for interrupt source TMU2
IPRA (7 to 4)
Bits 14 to 12 description added
Note: SDRAM can be specified only in area 2 and area 3. If
SDRAM is connected to only one area, SDRAM should be
specified for area 3. In this case area 2 should be specified
as normal space.
Note 5 added
Note: 5. The SDRAM bank active mode can only be used
for the CS3 space. (Refer to the explanation of the BACTV
bit in the SDRAM control register.)
Bits 31 to 18 description amended
Bit
31 to 8
Bits 31 to 18 description amended
Bit
31 to 8
Legend:
DMAC : Direct memory access controller
SCIF
ADC
USB
TMU
TPU
IRQ5−IRQ0
DMAC
: Serial communication interface (with FIFO)
: A/D converter
: USB interface
: Timer pulse unit
: 16-bit timer pulse unit
NMI
SCIF
TMU
ADC
USB
Bit
Name
Bit
Name
(Interrupt request)
16
6
Initial
Value
0
Initial
Value
0
Input/output
control
R/W
R
R/W
R
Description
Reserved
Description
Reserved

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