HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 597

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.2.9
BRCR sets the following conditions:
1. Specifies whether channels A and B are used in two independent channel conditions or under
2. Specifies whether a break is set before or after instruction execution.
3. Specifies whether to include the number of execution times on channel B in comparison
4. Specifies whether to include data bus on channel B in comparison conditions.
5. Enables PC trace.
6. Enables ASID check.
BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for
setting a variety of break conditions.
Bit
31 to 22
21
20
19 to 16
the sequential condition.
conditions.
Break Control Register (BRCR)
Bit
Name
BASMA
BASMB
Initial
Value
0
0
0
0
R/W
R
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Break ASID Mask A
Specifies whether bits in channel A break ASID7 to
ASID0 (BASA7 to BASA0) which are set in BASRA are
masked or not.
0: All BASRA bits are included in the break conditions
1: All BASRA bits are not included in the break conditions
Break ASID Mask B
Specifies whether bits in channel B break ASID7 to
ASID0 (BASB7 to BASB0) which are set in BASRB are
masked or not.
0: All BASRB bits are included in the break conditions
1: All BASRB bits are not included in the break conditions
Reserved
These bits are always read as 0. The write value should
always be 0.
and the ASID is checked
and the ASID is not checked
and the ASID is checked
and the ASID is not checked
Rev. 2.00, 09/03, page 549 of 690