HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 22

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.4
3.5
3.6
3.7
Section 4 Cache..............................................................................................93
4.1
4.2
4.3
4.4
4.5
Section 5 Exception Handling ........................................................................109
5.1
Rev. 2.00, 09/03, page xx of xlvi
3.3.2
3.3.3
3.3.4
MMU Functions .......................................................................................................... 81
3.4.1
3.4.2
3.4.3
3.4.4
MMU Exceptions ........................................................................................................ 85
3.5.1
3.5.2
3.5.3
3.5.4
Memory-Mapped TLB................................................................................................. 90
3.6.1
3.6.2
3.6.3
Usage Note .................................................................................................................. 92
Features....................................................................................................................... 93
4.1.1
Register Descriptions................................................................................................... 95
4.2.1
4.2.2
4.2.3
Operation .................................................................................................................... 101
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Memory-Mapped Cache............................................................................................... 104
4.4.1
4.4.2
4.4.3
Usage Note .................................................................................................................. 108
Register Descriptions................................................................................................... 109
5.1.1
5.1.2
TLB Indexing.................................................................................................. 77
TLB Address Comparison ............................................................................... 78
Page Management Information ........................................................................ 80
MMU Hardware Management ......................................................................... 81
MMU Software Management .......................................................................... 81
MMU Instruction (LDTLB)............................................................................. 82
Avoiding Synonym Problems .......................................................................... 83
TLB Miss Exception ....................................................................................... 85
TLB Protection Violation Exception ................................................................ 86
TLB Invalid Exception .................................................................................... 87
Initial Page Write Exception ............................................................................ 88
Address Array ................................................................................................. 90
Data Array ...................................................................................................... 90
Usage Examples.............................................................................................. 92
Cache Structure............................................................................................... 93
Cache Control Register 1 (CCR1).................................................................... 96
Cache Control Register 2 (CCR2).................................................................... 97
Cache Control Register 3 (CCR3).................................................................... 100
Searching the Cache ........................................................................................ 101
Read Access.................................................................................................... 102
Prefetch Operation .......................................................................................... 102
Write Access ................................................................................................... 102
Write-Back Buffer........................................................................................... 103
Coherency of Cache and External Memory ...................................................... 103
Address Array ................................................................................................. 104
Data Array ...................................................................................................... 105
Usage Examples.............................................................................................. 107
TRAPA Exception Register (TRA).................................................................. 110
Exception Event Register (EXPEVT) .............................................................. 111