HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 564

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20.7.2
PGDR is an 8-bit readable/writable register that stores data for pins PTG7 to PTG0. Bits PG7DT
to PG0DT correspond to pins PTG7 to PTG0. When the pin function is general output port, if the
port is read, the value of the corresponding PGDR bit is returned directly. When the function is
general input port, if the port is read the corresponding pin level is read.
Table 20.7 Port G Data Register (PGDR) Read/Write Operations
PGnMD1 PGnMD0 Pin State
0
1
Note: n = 0 to 7
20.8
Port H is a 7-bit input/output port with the pin configuration shown in figure 20.8. Each pin has an
input pull-up MOS, which is controlled by the port H control register (PHCR) in the PFC.
Rev. 2.00, 09/03, page 516 of 690
Bit
7 to
0
PGCR State
Bit
Name
PG7DT
to
PG0DT
Port G Data Register (PGDR)
Port H
0
1
0
1
Initial
Value
0
Other function PGDR value Data can be written to PGDR but no effect on
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
Port H
R/W
R/W
Read
PGDR value Written data is output from the pin.
Pin state
Pin state
Figure 20.8 Port H
PTH6 (input/output)/DREQ1 (input)
PTH5 (input/output)/DREQ0 (input)
PTH4 (input/output)/IRQ4 (input)
PTH3 (input/output)/IRQ3 (input)/IRL3 (input)
PTH2 (input/output)/IRQ2 (input)/IRL2 (input)
PTH1 (input/output)/IRQ1 (input)/IRL1 (input)
PTH0 (input/output)/IRQ0 (input)/IRL0 (input)
Description
Table 20.7 shows the function of PGDR.
Write
pin state.
Data can be written to PGDR but no effect on
pin state.
Data can be written to PGDR but no effect on
pin state.