HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 496

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.3.15 Trigger Register (TRG)
TRG generates one-shot triggers to control the transfer sequence for each endpoint.
Bit
7
6
5
4
3
2
1
0
Rev. 2.00, 09/03, page 448 of 690
Bit Name
EP3PKTE
EP1RDFN
EP2PKTE
EP0sRDFN
EP0oRDFN
EP0iPKTE
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
W
W
W
W
W
W
Description
Reserved
The write value should always be 0.
EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint
1 receive FIFO buffer has a dual-buffer
configuration. Writing 1 to this bit initializes the FIFO
that was read, enabling the next packet to be
received.
EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
Reserved
The write value should always be 0.
EP0s Read Complete
Write 1 to this bit after data for the EP0s command
FIFO has been read. Writing 1 to this bit enables
transfer of data in the following data stage. A NACK
handshake is returned in response to transfer
requests from the host in the data stage until 1 is
written to this bit.
EP0o Read Complete
Writing 1 to this bit after one packet of data has
been read from the endpoint 0 transmit FIFO buffer
initializes the FIFO buffer, enabling the next packet
to be received.
EP0i Packet Enable
After one packet of data has been written to the
endpoint 0 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.