HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 302

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.4.2
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by external devices and on-chip peripheral modules that are neither the
source nor the destination. Transfers can be requested in three modes: auto request, external
request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0
bits in the DMA channel control register (CHCR), and DMARS0 and DMARS1.
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bit in CHCR and the DME bit in DMAOR are set
to 1, the transfer begins so long as the AE and NMIF bits in DMAOR are 0.
External Request Mode: In this mode a transfer is performed at the request signals (DREQ0 and
DREQ1) of an external device. This mode is valid only in channels 0 and 1. Choose one of the
modes shown in table 8.3 according to the application system. When this mode is selected, if the
DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed
upon a request at the DREQ input.
Table 8.3
RS3
0
Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit
of CHCR_0 and CHCR_1 as shown in table 8.4. The source of the transfer request does not have
to be the data transfer source or destination.
Rev. 2.00, 09/03, page 254 of 690
RS2
0
DMA Transfer Requests
Selecting External Request Modes with RS Bits
RS1
0
1
RS0
0
0
1
Address Mode
Dual address
mode
Single address
mode
Source
Any
External memory,
memory-mapped
external device
External device with
DACK
Destination
Any
External device with
DACK
External memory,
memory-mapped
external device