HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 197

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.1
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. BSC functions enable this LSI to
connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.
7.1.1
The BSC has the following features:
BSCS311A_000020020100
Physical address space is divided into eight areas
Normal space interface
Burst ROM interface
Address/data multiplex I/O (MPX) interface
SDRAM interface
A maximum 32 or 64 Mbytes for each of the eight areas, CS0, CS2 to CS4, CS5A, CS5B,
CS6A and CS6B, totally 384 Mbytes.
Can specify the normal space interface, byte-selection SRAM interface, burst ROM,
address/data multiplex I/O (MPX), or SDRAM for each address space.
Can select the data bus width (8, 16, or 32 bits) for each address space.
Controls the insertion of the wait state for each address space.
Controls the insertion of the wait state for each read access and write access.
Can set the independent idling cycle in the continuous access for five cases: read-write (in
same space/different space), read-read (in same space/different space), the first cycle is a
write access.
Supports the interface that can directly connect to the SRAM.
High-speed access to the ROM, such as flash memory, that has the page mode function.
Can directly connect to a peripheral LSI that needs an address/data multiplexing.
Can set the SDRAM up to 2 areas.
Multiplex output for row address/column address.
Efficient access by single read/single write.
High-speed access by the bank-active mode.
Supports an auto-refresh and self-refresh.
Overview
Features
Section 7 Bus State Controller (BSC)
Rev. 2.00, 09/03, page 149 of 690