HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 93

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When an interrupt exception handling request is received for interrupts WKP
bit is set to 1. The vector number for interrupts WKP
assigned the same vector number, the interrupt source must be determined by the exception
handling routine.
Interrupts IRQ
IRQ
depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR).
When these pins are designated as pins IRQ
PMR2) and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an
interrupt. Interrupts IRQ
All interrupts can be masked by setting the I bit in CCR to 1.
When IRQ
to 8 are assigned to interrupts IRQ
(low). Table 3.2 gives details.
3.3.4
There are 20 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2
to 0. All interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt
request is accepted, the I bit is set to 1. Vector numbers 10 to 20 are assigned to these interrupts.
Table 3.2 shows the order of priority of interrupts from on-chip peripheral modules.
3.3.5
Interrupts are controlled by an interrupt controller. Figure 3.3 shows a block diagram of the
interrupt controller. Figure 3.4 shows the flow up to interrupt acceptance.
Interrupt operation is described as follows.
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When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to
table 3.2 for a list of interrupt priorities.)
The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is
accepted; if the I bit is 1, the interrupt request is held pending.
4
. These interrupts are detected by either rising edge sensing or falling edge sensing,
Internal Interrupts
Interrupt Operations
0
to IRQ
0
to IRQ
4
interrupt exception handling is initiated, the I bit is set to 1. Vector numbers 4
0
4
to IRQ
: Interrupts IRQ
4
can be disabled by clearing bits IEN0 to IEN4 in IENR1 to 0.
0
to IRQ
0
4
. The order of priority is from IRQ
to IRQ
0
to IRQ
4
are requested by into pins inputs to IRQ
4
0
in port mode registers 1 and 2 (PMR1 and
to WKP
7
is 9. Since all eight interrupts are
0
0
to WKP
(high) to IRQ
7
, the CCR I
0
to
4