HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 496

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SSR—Serial status register
Transmit data register empty
Note: Only a write of 0 for flag clearing is possible.
Bit
Initial value
Read/Write
0 Indicates that transmit data written to TDR has not been transferred to TSR
1 Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR
Receive data register full
0 Indicates there is no receive data in RDR
1 Indicates that there is receive data in RDR
[Clearing conditions]
[Setting conditions]
Overrun error
0 Indicates that data receiving is in progress or has been completed
1 Indicates that an overrun error occurred in data receiving
[Clearing conditions]
[Setting conditions]
Framing error
0 Indicates that data receiving is in progress or has been completed
1 Indicates that a framing error occurred in data receiving
*
[Clearing conditions]
[Setting conditions]
Parity error
0 Indicates that data receiving is in progress or has been completed
1 Indicates that a parity error occurred in data receiving
[Clearing conditions]
[Setting conditions]
Transmit end
0 Indicates that transmission is in progress
1 Indicates that a transmission has ended
[Clearing conditions]
[Setting conditions]
Multiprocessor bit receive
0 Indicates reception of data in which the multiprocessor bit is 0
1 Indicates reception of data in which the multiprocessor bit is 1
[Clearing conditions]
[Setting conditions]
TDRE
R/(W)
7
1
After reading TDRE = 1, cleared by writing 0.
When data is written to TDR by an instruction.
When bit TE in serial control register 3 (SCR3) is 0.
When data is transferred from TDR to TSR.
After reading RDRF = 1, cleared by writing 0.
When data is read from RDR by an instruction.
When receiving ends normally, with receive data transferred from RSR to RDR
After reading OER = 1, cleared by writing 0
When data receiving is completed while RDRF is set to 1
*
After reading FER = 1, cleared by writing 0
The stop bit at the end of receive data is checked and found to be 0
After reading PER = 1, cleared by writing 0
When the sum of 1s in received data plus the parity bit does not match
the parity mode bit (PM) setting in the serial mode register (SMR)
After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
When bit TE in serial control register 3 (SCR3) is 0.
If TDRE is set to 1 when the last bit of a transmitted character is sent.
RDRF
R/(W)
6
0
*
R/(W)
OER
5
0
*
R/(W)
FER
4
0
*
R/(W)
PER
3
0
Multiprocessor bit transmit
0 The multiprocessor bit in transmit data is 0
1 The multiprocessor bit in transmit data is 1
*
H'AC
TEND
R
2
1
MPBR
R
1
0
MPBT
R/W
0
0
SCI3
479