HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 277

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 3—Parity Error (PER): Bit 3 is a status flag indicating that a parity error has occurred during
asynchronous receiving.
Bit 3: PER
0
1
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, PER is unaffected and
Bit 2—Transmit End (TEND): Bit 2 is a status flag indicating that TDRE was set to 1 when the
last bit of a transmitted character was sent. TEND is a read-only bit and cannot be modified
directly.
Bit 2: TEND
0
1
Bit 1—Multiprocessor Bit Receive (MPBR): Bit 1 holds the multiprocessor bit in data received
in asynchronous mode using a multiprocessor format. MPBR is a read-only bit and cannot be
modified.
Bit 1: MPBR
0
1
Note: * If bit RE is cleared to 0 while a multiprocessor format is in use, MPBR retains its previous
260
state.
2. When a parity error occurs, receive data is transferred to RDR but RDRF is not set.
keeps its previous state.
While PER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
Description
Indicates that data receiving is in progress or has been completed
Clearing condition:
After reading PER = 1, cleared by writing 0 to PER
Indicates that a parity error occurred in data receiving
Setting condition:
When the sum of 1s in received data plus the parity bit does not match the parity
mode bit (PM) setting in the serial mode register (SMR)
Description
Indicates that transmission is in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
Indicates that a transmission has ended
Setting conditions:
When bit TE in SCR3 is cleared to 0.
If TDRE is set to 1 when the last bit of a transmitted character is sent.
Description
Indicates reception of data in which the multiprocessor bit is 0*
Indicates reception of data in which the multiprocessor bit is 1
*
2
*
1
(initial value)
(initial value)
(initial value)