HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 250

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Simultaneous transmit/receive: A simultaneous transmit/receive operation is carried out as
follows.
When an internal clock is used, a serial clock is output from pin SCK
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO
transmitted.
When an external clock is used, data is transmitted and received in synchronization with the serial
clock input at pin SCK
the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun
error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO
SCSR1.
Read the received data from SDRL and SDRU, as follows.
After data reception is complete, an overrun occurs if the serial clock continues to be input; no
data is received and the SCSR1 overrun error flag (bit ORER) is set to 1.
Set bits SO1, SI1, and SCK1 in PMR3 to 1 so that the respective pins function as SO
SCK
at pin SO
Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous
transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes
the internal state of SCI1.
Write transmit data in SDRL and SDRU, as follows.
Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO
Receive data is input at pin SI
After data transmission and reception are complete, bit IRRS1 in IRR1 is set to 1.
Read the received data from SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
1
. If necessary, set bit POF1 in port mode register 2 (PMR2) for NMOS open drain output
1
.
1
. After data transmission and reception are complete, an overrun occurs if
1
.
1
continues to output the value of the last bit
1
can be changed by rewriting bit SOL in
1
in synchronization with the
1
, SI
1
, and
233
1
.