HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 310

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Sending a Mark or Break Signal: When TE is cleared to 0 the TXD pin becomes an I/O port, the
level and direction (input or output) of which are determined by the PDR and PCR bits. This
feature can be used to place the TXD pin in the mark state or send a break signal.
To place the serial communication line in the mark (1) state before TE is set to 1, set the PDR and
PCR bits both to 1. Since TE is cleared to 0, TXD becomes a general output port outputting the
value 1.
To send a break signal during data transmission, set the PCR bit to 1 and clear the PDR bit to 0,
then clear TE to 0. When TE is cleared to 0 the transmitter is initialized, regardless of its current
state, so the TXD pin becomes an output port outputting the value 0.
Receive Error Flags and Transmit Operation (Sysnchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1, SCI3 will not start transmitting even if TDRE is
cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that
clearing RE to 0 does not clear the receive error flags.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous
mode SCI3 operates on a base clock with 16 times the bit rate frequency. In receiving, SCI3
synchronizes internally with the falling edge of the start bit, which it samples on the base clock.
Receive data is latched at the rising edge of the eighth base clock pulse. See figure 10.27.
Internal base
clock
Receive data
(RXD)
Synchronization
sampling timing
Data sampling
timing
Figure 10.27 Receive Data Sampling Timing in Asynchronous Mode
0
8 clock cycles
Start bit
16 clock cycles
7
15
0
D0
7
15 0
D1
293