HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 301

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Simultaneous Transmit/Receive: Figure 10.21 shows a typical flow chart for transmitting and
receiving simultaneously. After SCI3 synchronization, follow the procedure below.
284
1
2
3
Read received data in RDR
Figure 10.21 Simultaneous Transmit/Receive Flow Chart in Synchronous Mode
Write transmit data in TDR
Read bit TDRE in SSR
Read bit OER in SSR
Read RDRF in SSR
Clear bits TE and
RE in SCR3 to 0
transmitting and
TDRE = 1?
RDRF = 1?
receiving?
OER = 1?
Continue
Start
End
Yes
Yes
No
No
4
Overrun error processing
Yes
Yes
No
No
1.
2.
3.
4.
Read the serial status register (SSR),
and after confirming that bit TDRE = 1,
write transmit data in the transmit data
register (TDR). When data is written to
TDR, TDRE is automatically cleared to 0.
Read the serial status register (SSR),
and after confirming that bit RDRF = 1,
read the received data from the receive
data register (RDR). When data is read
from RDR, RDRF is automatically cleared
to 0.
To continue transmitting and receiving
serial data, read bit RDRF and finish
reading RDR before the MSB (bit 7) of the
present frame is received. Also read bit
TDRE, check that it is set to 1, and write
the next data in TDR before the MSB of
the current frame has been transmitted.
When data is written to TDR, TDRE is
automatically cleared to 0; and when data
is read from RDR, RDRF is automatically
cleared to 0.
When an overrun error occurs, read bit
OER in SSR. After the necessary error
processing, be sure to clear OER to 0.
Data transmission and reception cannot
take place while bit OER is set to 1. See
figure 10.19 for overrun error processing.