HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 270

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 6—Character Length (CHR): Bit 6 selects either 7 bits or 8 bits as the data length in
asynchronous mode. In synchronous mode the data length is always 8 bits regardless of the setting
here.
Bit 6: CHR
0
1
Note: * When 7-bit data is selected as the character length in asynchronous mode, the MSB (bit 7)
Bit 5—Parity Enable (PE): In asynchronous mode, bit 5 selects whether or not a parity bit is to
be added to transmitted data and checked in received data. In synchronous mode there is no adding
or checking of parity regardless of the setting here.
Bit 5: PE
0
1
Note: * When PE is set to 1, then either odd or even parity is added to transmit data, depending on
Bit 4—Parity Mode (PM): In asynchronous mode, bit 4 selects whether odd or even parity is to
be added to transmitted data and checked in received data. The PM setting is valid only if bit PE is
set to 1, enabling parity adding/checking. In synchronous mode, or if parity adding/checking is
disabled in asynchronous mode, the PM setting is invalid.
Bit 4: PM
0
1
Notes: 1. When even parity is designated, a parity bit is added to the transmitted data so that the
in the transmit data register is not transmitted.
the setting of the parity mode bit (PM). When data is received, it is checked for odd or even
parity as designated in bit PM.
2. When odd parity is designated, a parity bit is added to the transmitted data so that the
sum of 1s in the resulting data is an even number. When data is received, the sum of 1s
in the data plus parity bit is checked to see if the result is an even number.
sum of 1s in the resulting data is an odd number. When data is received, the sum of 1s
in the data plus parity bit is checked to see if the result is an odd number.
Description
8-bit data
7-bit data*
Description
Parity bit adding and checking disabled
Parity bit adding and checking enabled*
Description
Even parity
Odd parity
*
*
2
1
(initial value)
(initial value)
(initial value)
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