HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 218

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 2: CKSL2
0
1
Note: 1. The edge of the external event signal is selected by bit IEG3 in the IRQ edge select
Timer Control/Status Register F (TCSRF)
Note: * Only 0 can be written, to clear flag.
TCSRF is an 8-bit read/write register. It is used for counter clear selection, overflow and compare
match indication, and enabling of interrupts caused by timer overflow.
Upon reset, TCSRF is initialized to H'00.
Bit 7—Timer overflow flag H (OVFH): Bit 7 is a status flag indicating TCFH overflow (H'FF to
H'00). This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 7: OVFH
0
1
Bit 6—Compare Match Flag H (CMFH): Bit 6 is a status flag indicating a compare match
between TCFH and OCRFH. This flag is set by hardware and cleared by software. It cannot be set
by software.
Bit
Initial value
Read/Write
* Don’t care
register (IEGR). See 3.3.2, for details on the IRQ edge select register. Note that
switching the TMIF pin function by changing bit IRQ3 in port mode register 1 (PMR1)
from 0 to 1 or from 1 to 0 while the TMIF pin is at the low level may cause the timer F
counter to be incremented.
Bit 1: CKSL1
*
0
1
OVFH
R/W*
Description
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
Setting conditions:
Set when the value of TCFH goes from H'FF to H'00
7
0
CMFH
R/W*
6
0
Bit 0: CKSL0
*
0
1
0
1
OVIEH
R/W
5
0
CCLRH
R/W
4
0
Description
External event (TMIF). Rising or falling edge
is counted*
Internal clock: /32
Internal clock: /16
Internal clock: /4
Internal clock: /2
R/W*
OFL
3
0
1
CMFL
R/W*
2
0
OVIEL
R/W
1
0
(initial value)
(initial value)
CCLRL
R/W
0
0
201