HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 276

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 5—Overrun Error (OER): Bit 5 is a status flag indicating that an overrun error has occurred
during data receiving.
Bit 5: OER
0
1
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, OER is unaffected and
Bit 4—Framing Error (FER): Bit 4 is a status flag indicating that a framing error has occurred
during asynchronous receiving.
Bit 4: FER
0
1
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, FER is unaffected and
2. RDR keeps the data received prior to the overrun; data received after that is lost. While
2. When two stop bits are used only the first stop bit is checked, not the second. When a
keeps its previous state.
OER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
keeps its previous state.
framing error occurs, receive data is transferred to RDR but RDRF is not set. While
FER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
Description
Indicates that data receiving is in progress or has been completed
Clearing condition:
After reading OER = 1, cleared by writing 0 to OER
Indicates that an overrun error occurred in data receiving
Setting condition:
When data receiving is completed while RDRF is set to 1
Description
Indicates that data receiving is in progress or has been completed
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
Indicates that a framing error occurred in data receiving
Setting condition:
The stop bit at the end of receive data is checked for a value of 1 and found to be
0*
2
*
2
*
*
1
1
(initial value)
(initial value)
259