HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 89

MCU 5V 32K PB-FREE 100-QFP

HD6473834HV

Manufacturer Part Number
HD6473834HV
Description
MCU 5V 32K PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD6473834HV

Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
71
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473834HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473834HV
Manufacturer:
RENESAS
Quantity:
2 120
Interrupt request register 1 (IRR1)
Note: * Only a write of 0 for flag clearing is possible.
IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A,
SCI1, or IRQ
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7—Timer A Interrupt Request Flag (IRRTA)
Bit 7: IRRTA
0
1
Bit 6—SCI1 Interrupt Request Flag (IRRS1)
Bit 6: IRRS1
0
1
Bit 5—Reserved Bit: Bit 5 is reserved; it is always read as 1, and cannot be modified.
Bits 4 to 0—IRQ
Bit n: IRRIn
0
1
72
Bit
Initial value
Read/Write
4
to IRQ
4
IRRTA
R/W*
to IRQ
Description
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
Setting conditions:
When the timer A counter value overflows (goes from H'FF to H'00)
Description
Clearing conditions:
When IRRS1 = 1, it is cleared by writing 0
Setting conditions:
When an SCI1 transfer is completed
Description
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0 to IRRIn
Setting conditions:
IRRIn is set when pin IRQ
edge is detected
7
0
0
interrupt is requested. The flags are not cleared automatically when an
0
Interrupt Request Flags (IRRI4 to IRRI0)
IRRS1
R/W*
6
0
5
1
n
is set to interrupt input, and the designated signal
IRRI4
R/W*
4
0
IRRI3
R/W*
3
0
IRRI2
R/W*
2
0
IRRI1
R/W*
1
0
(initial value)
(initial value)
(initial value)
(n = 4 to 0)
IRRI0
R/W*
0
0

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