HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 271

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 3—Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length in
asynchronous mode. This setting is valid only in asynchronous mode. In synchronous mode a stop
bit is not added, so this bit is ignored.
Bit 3: STOP
0
1
Notes: 1. When data is transmitted, one 1 bit is added at the end of each transmitted character as
When data is received, only the first stop bit is checked regardless of the stop bit length. If the
second stop bit value is 1 it is treated as a stop bit; if it is 0, it is treated as the start bit of the next
character.
Bit 2—Multiprocessor Mode (MP): Bit 2 enables or disables the multiprocessor communication
function. When the multiprocessor communication function is enabled, the parity enable (PE) and
parity mode (PM) settings are ignored. The MP bit is valid only in asynchronous mode; it should
be cleared to 0 in synchronous mode.
See 10.4.6, for details on the multiprocessor communication function.
Bit 2: MP
0
1
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0): Bits 1 and 0 select the clock source for the built-
in baud rate generator. A choice of /64, /16, /4, or is made in these bits.
See 8, Bit rate register (BRR), below for information on the clock source and bit rate register
settings, and their relation to the baud rate.
Bit 1: CKS1
0
1
254
2. When data is transmitted, two 1 bits are added at the end of each transmitted character
the stop bit.
as the stop bits.
Description
1 stop bit
2 stop bits
Description
Multiprocessor communication function disabled
Multiprocessor communication function enabled
Bit 0: CKS0
0
1
0
1
*
1
*
2
Description
/4 clock
/16 clock
/64 clock
clock
(initial value)
(initial value)
(initial value)