HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 832

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Registers
Rev. 4.00 Jan 26, 2006 page 808 of 938
REJ09B0276-0400
DRCRA—DRAM Control Register A
Initial value
Read/Write
Bit
Note: * A single CSn pin serves as a common RAS output pin for a number of
DRAM area select
DRAS2 DRAS1 DRAS0
DRAS2
R/W
0
1
7
0
areas. Unused CSn pins can be used as input/output ports.
Burst access enable
DRAS1
0
1
R/W
6
0
RAS down mode
0
1
0
1
0
1
Burst disabled (always full access)
DRAM space access performed in fast page mode
DRAS0
DRAM interface: RAS up mode selected
DRAM interface: RAS down mode selected
Self-refresh mode
R/W
0
1
5
0
0
1
0
1
0
1
0
1
Refresh pin enable
0
1
DRAM self-refreshing is disabled in
software standby mode
DRAM self-refreshing is enabled
in software standby mode
DRAM space
RFSH pin refresh signal output is disabled
RFSH pin refresh signal output is enabled
4
1
Normal
Normal
Normal
Normal
Normal
Area 5
(CS
DRAM space(CS
5
)
R/W
BE
3
0
DRAM space
DRAM space
Normal
Normal
Normal
Normal
Area 4
(CS
(CS
DRAM space(CS
RDM
R/W
H’EE026
2
0
4
4
4
)
)*
)
SRFMD
DRAM space
DRAM space
DRAM space
R/W
1
0
Normal
Normal
Area 3
(CS
(CS
(CS
DRAM space(CS
DRAM space(CS
2
3
3
3)
)*
RFSHE
)
)
R/W
0
0
DRAM space
DRAM space
DRAM space
DRAM space
DRAM interface
Normal
Area 2
(CS
(CS
(CS
(CS
2
2
)*
2
2
2
2
)*
)
)
)
)