HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 225

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall
(assertion) of CSn may occur simultaneously. An example of the operation is shown in figure
6.47.
If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in
BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0
bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following
bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,
it is possible that the low-level output of RD in the preceding read cycle and the low-level output
of CSn in the following bus cycle will overlap.
(UCAS/LCAS)
Address bus
HWR/LWR
Figure 6.45 Example of Idle Cycle Operation (3) (HWR
Figure 6.46 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)
CSn
(a) Idle cycle not inserted
(DRAM access cycle)
Tp
Bus cycle A
UCAS/LCAS
Address bus
Address bus
Tr Tc1 Tc2
Simultaneous change of
HWR/LWR and CSn
RD
Bus cycle B
T1
T1
External read
T2
T2
(UCAS/LCAS)
T3
Address bus
HWR/LWR
Tp
DRAM space read
Rev. 4.00 Jan 26, 2006 page 201 of 938
CSn
HWR/LWR
HWR
HWR
Tr
(DRAM access cycle) Bus cycle B
LWR Used as UCAS
LWR
LWR
Tc1
Tp
Bus cycle A
(b) Idle cycle inserted
Tr Tc1 Tc2
Tc2
Section 6 Bus Controller
UCAS/LCAS
UCAS
UCAS
REJ09B0276-0400
Ti
LCAS)
LCAS
LCAS
T1
T2