HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 546

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 13 Serial Communication Interface
In transmitting serial data, the SCI operates as follows:
Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format.
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REJ09B0276-0400
TDRE
TEND
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit,
then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-
end interrupt (TEI) is requested at this time
Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
1
TXI interrupt
request
Start bit: One 0 bit is output.
Transmit data: 7 or 8 bits are output, LSB first.
Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
Stop bit(s): One or two 1 bits (stop bits) are output.
Mark state: Output of 1 bits continues until the start bit of the next transmit data.
Start
bit
0
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Figure 13.11 Example of SCI Transmit Operation
D1
1 frame
Data
D7
processor
Multi-
TXI interrupt
request
0/1
bit
Stop
bit
1
Start
bit
0
D0
D1
Data
D7
processor
Multi-
bit
0/1
request
Stop
bit
TEI interrupt
1
state
Idle (mark)