HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 346

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 I/O Ports
Pin
PB
TMIO
DREQ
PB
TMO
Rev. 4.00 Jan 26, 2006 page 322 of 938
REJ09B0276-0400
3
2
/TP
/TP
2
3
/CS
/
1
11
/CS
10
/
/
5
4
Pin Functions and Selection Method
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in TCSR3, bits
CCLR1 and CCLR0 in TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB
function as follows.
DRAM interface
settings
OIS3/2 and OS1/0
CS4E
PB
NDER11
Pin function
Notes:
DRAM interface
settings
DRAS2
DRAS1
DRAS0
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in TCSR2, bit
CS5E in CSCR, bit NDER10 in NDERB, and bit PB
DRAM interface
settings
OIS3/2 and OS1/0
CS5E
PB
NDER10
Pin function
Note: *
DRAM interface
settings
DRAS2
DRAS1
DRAS0
3
2
DDR
DDR
CS
1.
2.
3.
5
is output as RAS
TMIO
When an external request is specified as a DMAC activation source, DREQ
bits OIS3 and OIS2, OS1 and OS0, CCLR1 and CCLR0, CS4E, NDER11, and PB
CS
4
is output as RAS
3
input when CCLR1 = CCLR0 = 1.
input
0
input
0
PB
PB
—
—
0
0
5
.
3
2
0
0
4
.
1
1
output
output
PB
PB
(1)
0
1
0
0
0
1
0
0
3
2
(1)
0
0
All 0
All 0
2
(1) in table below
(1) in table below
DDR select the pin function as follows.
1
1
output
output
TP
TP
1
1
1
1
DREQ
TMIO
11
10
1
1
3
1
input *
input *
output
output
0
0
CS
CS
—
—
—
—
1
1
2
1
4
5
0
0
(2)
(2)
TMIO
TMIO
1
1
3
DDR select the pin
Not all 0
Not all 0
—
—
—
—
—
—
3
2
1
1
output
output
1
input regardless of
0
0
3
DDR.
(2) in table
(2) in table
(1)
1
1
output *
output*
below
below
CS
CS
—
—
—
—
—
—
—
—
(1)
1
4
1
5
3