HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 435

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination
with the ICE bit in TCSR1 (TCSR3), these bits select the compare match B output level or the
input capture input detected edge.
The function of TCORB1 (TCORB3) depends on the setting of bit 4 of TCSR1 (TCSR3).
TCORB0 and TCORB2 function as compare match registers regardless of the setting of bit 4 of
TCSR1 (TCSR3).
ICE Bit in
TCSR1
(TCSR3)
0
1
Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1
0
1
When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
Bit 0
OS0
0
1
0
1
Bit 3
OIS3
0
1
0
1
Bit 2
OIS2 Description
0
1
0
1
0
1
0
1
Description
No change when compare match A occurs
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A occurs (toggle output)
No change when compare match B occurs
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B occurs (toggle output)
TCORB input capture on rising edge
TCORB input capture on falling edge
TCORB input capture on both rising and falling edges
Rev. 4.00 Jan 26, 2006 page 411 of 938
Section 10 8-Bit Timers
REJ09B0276-0400
(Initial value)
(Initial value)