HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet
HD64F3067RF20
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HD64F3067RF20 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/3067 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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The H8/3067 Group is a series of high-performance single-chip microcontrollers that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set ...
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Rev. 4.00 Jan 26, 2006 page iv of xxii ...
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Main Revisions in This Edition Item Page All 1.1 Overview 6 Table 1.1 Features 1.4.2 Product Type — Names and Markings 6.3.5 Address 150 Output Method 7.2.2 I/O Address 215 Registers (IOAR) 7.4.2 I/O Mode 231 Table 7.6 Register Functions ...
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Item Page 7.4.3 Idle Mode 234 Table 7.7 Register Functions in Idle Mode 7.4.4 Repeat Mode 237 Table 7.8 Register Functions in Repeat Mode 18.4 On-Board 621 Programming Modes Table 18.6 Setting On-Board Programming Modes B.2 Functions 803 ADRCR Appendix ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 10 1.3.3 Pin Assignments in Each Mode ........................................................................... 16 1.4 Notes on Flash Memory R Version Model ....................................................................... 21 ...
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Exception-Handling Sequences ........................................................................... 57 2.8.5 Bus-Released State............................................................................................... 58 2.8.6 Reset State............................................................................................................ 58 2.8.7 Power-Down State ............................................................................................... 59 2.9 Basic Operational Timing ................................................................................................. 60 2.9.1 Overview.............................................................................................................. 60 2.9.2 On-Chip Memory Access Timing........................................................................ 60 2.9.3 On-Chip Supporting Module Access Timing ...................................................... ...
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Section 5 Interrupt Controller 5.1 Overview........................................................................................................................... 91 5.1.1 Features................................................................................................................ 91 5.1.2 Block Diagram ..................................................................................................... 92 5.1.3 Pin Configuration................................................................................................. 93 5.1.4 Register Configuration......................................................................................... 93 5.2 Register Descriptions ........................................................................................................ 94 5.2.1 System Control Register (SYSCR) ...................................................................... 94 5.2.2 Interrupt Priority Registers A ...
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Refresh Timer Counter (RTCNT)........................................................................ 141 6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 142 6.2.12 Address Control Register (ADRCR) (Provided Only in Flash Memory R Version and Mask ROM Versions) ............ 143 6.3 Operation .......................................................................................................................... 144 6.3.1 Area Division ....................................................................................................... ...
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Bus Arbiter........................................................................................................................ 203 6.10.1 Operation ............................................................................................................. 203 6.11 Register and Pin Input Timing .......................................................................................... 206 6.11.1 Register Write Timing ......................................................................................... 206 6.11.2 BREQ Pin Input Timing ...................................................................................... 207 Section 7 DMA Controller 7.1 Overview........................................................................................................................... 209 7.1.1 Features................................................................................................................ 209 7.1.2 ...
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DMAC Self-Access ............................................................................................. 263 7.6.3 Longword Access to Memory Address Registers ................................................ 263 7.6.4 Note on Full Address Mode Setup ....................................................................... 263 7.6.5 Note on Activating DMAC by Internal Interrupts ............................................... 264 7.6.6 NMI Interrupts and Block Transfer Mode ...
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Port B ................................................................................................................................ 317 8.12.1 Overview.............................................................................................................. 317 8.12.2 Register Descriptions ........................................................................................... 319 Section 9 16-Bit Timer ....................................................................................................... 327 9.1 Overview........................................................................................................................... 327 9.1.1 Features................................................................................................................ 327 9.1.2 Block Diagrams ................................................................................................... 330 9.1.3 Input/Output Pins ................................................................................................. 333 9.1.4 Register Configuration......................................................................................... 334 9.2 ...
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Block Diagram ..................................................................................................... 399 10.1.3 Pin Configuration................................................................................................. 400 10.1.4 Register Configuration......................................................................................... 401 10.2 Register Descriptions ........................................................................................................ 402 10.2.1 Timer Counters (TCNT) ...................................................................................... 402 10.2.2 Time Constant Registers A (TCORA) ................................................................. 403 10.2.3 Time Constant Registers B (TCORB).................................................................. 404 10.2.4 ...
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Register Descriptions ........................................................................................................ 439 11.2.1 Port A Data Direction Register (PADDR) ........................................................... 439 11.2.2 Port A Data Register (PADR) .............................................................................. 439 11.2.3 Port B Data Direction Register (PBDDR)............................................................ 440 11.2.4 Port B Data Register (PBDR) .............................................................................. 440 11.2.5 Next ...
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Section 13 Serial Communication Interface 13.1 Overview........................................................................................................................... 477 13.1.1 Features................................................................................................................ 477 13.1.2 Block Diagram ..................................................................................................... 479 13.1.3 Input/Output Pins ................................................................................................. 480 13.1.4 Register Configuration......................................................................................... 481 13.2 Register Descriptions ........................................................................................................ 482 13.2.1 Receive Shift Register (RSR) .............................................................................. 482 13.2.2 Receive Data ...
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Transmitting and Receiving Data ........................................................................ 558 14.4 Usage Notes ...................................................................................................................... 566 Section 15 A/D Converter 15.1 Overview........................................................................................................................... 569 15.1.1 Features................................................................................................................ 569 15.1.2 Block Diagram ..................................................................................................... 570 15.1.3 Input Pins ............................................................................................................. 571 15.1.4 Register Configuration......................................................................................... 572 15.2 Register Descriptions ........................................................................................................ ...
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Section 18 ROM .................................................................................................................. 607 18.1 Overview........................................................................................................................... 607 18.2 Overview of Flash Memory .............................................................................................. 608 18.2.1 Features................................................................................................................ 608 18.2.2 Block Diagram ..................................................................................................... 609 18.2.3 Pin Configuration................................................................................................. 610 18.2.4 Register Configuration......................................................................................... 610 18.3 Register Descriptions ........................................................................................................ 611 18.3.1 Flash Memory Control ...
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Section 19 Clock Pulse Generator 19.1 Overview........................................................................................................................... 665 19.1.1 Block Diagram ..................................................................................................... 666 19.2 Oscillator Circuit............................................................................................................... 667 19.2.1 Connecting a Crystal Resonator........................................................................... 667 19.2.2 External Clock Input ............................................................................................ 669 19.3 Duty Adjustment Circuit................................................................................................... 672 19.4 Prescalers .......................................................................................................................... 672 19.5 Frequency ...
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Absolute Maximum Ratings ................................................................................ 695 21.1.2 DC Characteristics ............................................................................................... 696 21.1.3 AC Characteristics ............................................................................................... 706 21.1.4 A/D Conversion Characteristics........................................................................... 714 21.1.5 D/A Conversion Characteristics........................................................................... 716 21.2 Electrical Characteristics of Flash Memory and Flash Memory R Versions .................... 717 21.2.1 ...
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C.10 Port A Block Diagrams ..................................................................................................... 903 C.11 Port B Block Diagrams ..................................................................................................... 906 Appendix D Pin States D.1 Port States in Each Mode .................................................................................................. 914 D.2 Pin States at Reset ............................................................................................................. 921 Appendix E Timing of Transition to and ...
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Rev. 4.00 Jan 26, 2006 page xxii of xxii ...
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Overview The H8/3067 Group is a group of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, ...
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Section 1 Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation Maximum clock rate: 20 ...
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Feature Description Bus controller Address space can be partitioned into eight areas, with independent bus specifications in each area Chip select output available for areas 8-bit access or 16-bit access selectable for each area Two-state or three-state ...
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Section 1 Overview Feature Description 8-bit timer, 8-bit up-counter (external event count capability) 4 channels Two time constant registers Two channels can be connected Programmable Maximum 16-bit pulse output, using 16-bit timer as time base timing pattern Up to four ...
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Feature Description Operating modes Seven MCU operating modes Mode Address Space A ddress Pins Mode 1 1 Mbyte Mode 2 1 Mbyte Mode 3 16 Mbytes Mode 4 16 Mbytes Mode 5 16 Mbytes Mode 6 64 kbyte Mode 7 ...
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Section 1 Overview Feature Description Product Product Type lineup H8/3067 On-chip flash memory On-chip mask ROM H8/3066 On-chip mask ROM H8/3065 On-chip mask ROM Rev. 4.00 Jan 26, 2006 page 6 of 938 REJ09B0276-0400 Product Code 5 VR HD64F3067RF HD64F3067RTE ...
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Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES FWE*/RESO NMI /P6 7 LWR/P6 6 HWR/P6 5 RD/P6 4 AS/P6 3 BACK/P6 2 BREQ/P6 1 WAIT/ /P8 ...
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Section 1 Overview 1.3 Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3067 Group PRQP0100KA-A and PTQP0100KA-A packages is shown in figure 1.2, and that of the PRQP0100JE-B package in figure 1. REF ...
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/AN / /AN / ...
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Section 1 Overview 1.3.2 Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Pin No. PRQP 0100KA-A PTQP Type Symbol 0100KA-A Power 11, 22, 44, SS 57, 65, 92 Clock XTAL ...
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Pin No. PRQP 0100KA-A PTQP Type Symbol 0100KA-A Operating mode MD 0 control RES System 63 control RESO 10 FWE 10 STBY 62 BREQ 59 BACK 60 Interrupts NMI 64 IRQ to 17, 16, ...
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Section 1 Overview Pin No. PRQP 0100KA-A PTQP Type Symbol 0100KA-A Address 100 bus Data bus 23 ...
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Pin No. PRQP 0100KA-A PTQP Type Symbol 0100KA-A 16-bit TCLKD timer to TCLKA TIOCA 99, 97 TIOCA 0 TIOCB 100, 98 100, 98 Input TIOCB 0 8-bit timer TMO , ...
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Section 1 Overview Pin No. PRQP 0100KA-A PTQP Type Symbol 0100KA-A A/D and D/A converters REF I/O ports ...
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Pin No. PRQP 0100KA-A PTQP Type Symbol 0100KA-A I/O ports PA to 100 PRQP 0100JE-B I/O Name and Function 2, 1, Input/ Port A: Eight input/output pins. ...
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Section 1 Overview 1.3.3 Pin Assignments in Each Mode Table 1.3 lists the pin assignments in each mode. Table 1.3 Pin Assignments in Each Mode (PRQP0100KA-A or PTQP0100KA-A, PRQP0100JE-B) Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode ...
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Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode /IRQ / 5 5 SCK ...
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Section 1 Overview Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode ...
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Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode REF / / / / ...
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Section 1 Overview Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode / TIOCA 2 100 TIOCB 2 Notes modes ...
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Notes on Flash Memory R Version Model There are two models with on-chip flash memory in the H8/3067 Group: the flash memory version (HD64F3067) and the flash memory R version (HD64F3067R). Points to be noted when using the flash ...
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Section 1 Overview Rev. 4.00 Jan 26, 2006 page 22 of 938 REJ09B0276-0400 ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU High-speed operation All frequently-used instructions execute in two to four states Maximum clock frequency: 8/16/32-bit register-register add/subtract: 100 ns 8 8-bit register-register multiply: 16 ÷ 8-bit register-register divide: 16 16-bit register-register multiply: 1.1 µs 32 ÷ 16-bit ...
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CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. CPU operating modes Normal mode Advanced mode Figure 2.1 CPU Operating ...
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Section 2 CPU 2.3 Address Space Figure 2.2 shows a simple memory map for the H8/3067 Group. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in ...
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Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control ...
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Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as ...
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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...
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Section 2 CPU Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Section 2 CPU General Data Type Register Data Format Word data Rn 15 Word data En MSB 31 Longword data ERn MSB Legend ERn: General register En: General register E Rn: General register R MSB: Most significant bit LSB: Least ...
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Data Type 1-bit data Byte data Word data Longword data When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Address 7 Address Address ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction MOV, PUSH * Data transfer Arithmetic operations ADD, SUB, ADDX, ...
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Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Function Instruction #xx Rn Data MOV BWL BWL transfer POP, PUSH — — MOVFPE, — — MOVTPE Arithmetic ADD, ...
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Section 2 CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation Rd General register (destination)* Rs General register ...
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Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Cannot be used in this ...
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Section 2 CPU Table 2.4 Arithmetic Operation Instructions Instruction Size* Function ADD,SUB B/W/L Rd ± Rs Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Immediate byte data cannot ...
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Instruction Size* Function EXTS W/L Rd (sign extension) Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by ...
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Section 2 CPU Table 2.6 Shift Instructions Instruction Size* Function SHAL, B/W/L Rd (shift) SHAR Performs an arithmetic shift on general register contents. SHLL, B/W/L Rd (shift) SHLR Performs a logical shift on general register contents. ROTL, B/W/L Rd (rotate) ...
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Table 2.7 Bit Manipulation Instructions Instruction Size* Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 ...
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Section 2 CPU Instruction Size* Function BIXOR B C [¬ (<bit-No.> of <EAd>)] Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The ...
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Table 2.8 Branching Instructions Instruction Size Function Bcc — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC ...
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Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling RTE — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state LDC B/W (EAs) Moves the source operand ...
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Table 2.10 Block Transfer Instruction Instruction Size Function EEPMOV.B — if R4L repeat until else next; EEPMOV.W — then repeat until else next; Block transfer instruction. This instruction transfers the number of data bytes specified by R4L ...
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Section 2 CPU Operation field only Operation field and register fields op Operation field, register fields, and effective address extension op Operation field, effective address extension, and condition field op cc 2.6.5 Notes on Use of Bit Manipulation Instructions The ...
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Before Execution of BCLR Instruction Input/output Input Input DDR 0 0 Execution of BCLR Instruction BCLR #0, @P4DDR ;Clear bit 0 in data direction register After Execution of BCLR Instruction Input/output Output ...
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Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use ...
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the ...
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Section 2 CPU 7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the ...
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Section 2 CPU 2.8 Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby ...
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Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, ...
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Section 2 CPU Reset Exception Interrupt sources Trap instruction Figure 2.12 Classification of Exception Sources End of bus release Bus-released state End of exception handling Exception-handling state RES = "High" 1 Reset state* Notes: 1. From any state except hardware ...
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Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception ...
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Section 2 CPU Stack area SP (ER7) Before exception handling starts Legend CCR: Condition code register SP: Stack pointer Notes the address of the first instruction executed after the ...
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Power-Down State In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction ...
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Section 2 CPU 2.9 Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock ( ). The interval from one rise of the system clock to the next rise is referred “state.” A ...
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Address bus HWR LWR , , Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus ...
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Section 2 CPU Address bus HWR LWR , , Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3067 Group has seven operating modes (modes that are selected by the mode pins ( indicated in table 3.1. The input ...
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Section 3 MCU Operating Modes Mode externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 16 Mbytes. Modes ...
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Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3067 Group. Bit 7 Initial value 1 Read/Write Reserved bits Note: Determined by pins Bits 7 ...
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Section 3 MCU Operating Modes 3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3067 Group. Bit 7 6 SSBY STS2 STS1 Initial value 0 0 Read/Write R/W R/W Standby timer select 2 ...
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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by ...
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Section 3 MCU Operating Modes Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS bus control signals (CS 0 outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit ...
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are valid when 0 is written in bits the bus release control register 23 21 (BRCR). (In this mode A is always used for address output.) 20 3.4.4 Mode 4 Ports ...
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Section 3 MCU Operating Modes 3.5 Pin Functions in Each Operating Mode The pin functions of ports and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 ...
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Memory Map in Each Operating Mode Figure 3.1 to 3.3 show a memory maps of the H8/3067, H8/3066, and H8/3065. The address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 On-chip I/O ...
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Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM H'007FFF H'01FFFF H'020000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address Area 3 space H'7FFFFF H'800000 Area 4 H'9FFFFF ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 On-chip ...
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Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM H'007FFF H'017FFF H'018000 1 Reserved* H'01FFFF H'020000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address Area 3 space H'7FFFFF ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 On-chip I/O ...
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Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM H'007FFF H'00FFFF H'010000 1 Reserved* H'01FFFF H'020000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address Area 3 space H'7FFFFF ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset Exception • ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ 0 External interrupt IRQ 1 External interrupt IRQ 2 External interrupt IRQ 3 External interrupt IRQ 4 External ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and ...
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Figure 4.2 Reset Sequence (Modes 1 and 3) Section 4 Exception Handling Rev. 4.00 Jan 26, 2006 page 83 of 938 REJ09B0276-0400 ...
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Section 4 Exception Handling RES Address bus RD HWR , LWR High (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) ...
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RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1) Address of reset vector (H'0000) (2) Start address (contents of reset exception handling vector address) (3) First instruction of program Figure 4.4 Reset ...
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Section 4 Exception Handling 4.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ 36 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set the system control register (SYSCR), the exception handling sequence sets the I bit CCR. ...
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Section 4 Exception Handling 4.5 Stack Status after Exception Handling Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP–4 SP–3 SP–2 SP–1 SP (ER7) Stack area Before exception handling SP–4 SP–3 SP–2 ...
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Notes on Stack Usage When accessing word data or longword data, the H8/3067 Group regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack ...
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Section 4 Exception Handling SP TRAPA instruction executed SP set to H'FFFEFF Legend CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: The diagram illustrates modes 3 and 4. Figure 4.7 Operation when SP ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input section ISR OVF TME . . . . . . . . . . TEI TEIE Interrupt controller ...
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Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Nonmaskable interrupt External interrupt request Note the flash memory and flash memory R versions, NMI input is sometimes disabled. For details ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables ...
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI ...
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Section 5 Interrupt Controller Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 IPRA6 Initial value 0 Read/Write R/W R/W Priority level A6 Selects the priority level ...
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Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7 IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) 0 Bit 6—Priority Level ...
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Section 5 Interrupt Controller Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests. Bit 3 IPRA3 Description 0 WDT, DRAM interface, and A/D converter interrupt requests have priority level 0 (low ...
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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 6 IPRB7 IPRB6 Initial value 0 0 Read/Write R/W R/W Priority level B6 Selects the priority level of 8-bit ...
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Section 5 Interrupt Controller Bit 7—Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt requests. Bit 7 IPRB7 Description 0 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value) ...
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Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit 2 IPRB2 Description 0 SCI1 interrupt requests have priority level 0 (low priority) 1 SCI1 interrupt requests have priority level 1 (high priority) Bit ...
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Section 5 Interrupt Controller 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ requests. Bit 7 Initial value 0 Read/Write Reserved bits Note: * Only 0 can be written, to clear flags. ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ Bit 7 Initial value 0 Read/Write R/W R/W Reserved bits IER is initialized to H' reset and in hardware standby mode. Bits ...
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Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ . 5 0 Bit 7 Initial value 0 Read/Write ...
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Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, ...
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Section 5 Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector ...
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Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 Reserved WOVI Watchdog (interval timer) timer CMI DRAM (compare match) interface Reserved ADI (A/D ...
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Section 5 Interrupt Controller Interrupt Source Origin IMIA2 16-bit timer (compare match/ channel 2 input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved CMIA0 8-bit timer (compare match channel 0/1 A0) CMIB0 (compare match B0) CMIA1/CMIB1 ...
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Interrupt Source Origin ERI0 SCI (receive error 0) channel 0 RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI (receive error 1) channel 1 RXI1 (receive data full 1) TXI1 (transmit data empty ...
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Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3067 Group handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When ...
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Program execution state Interrupt requested? Yes No Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes TEI2 Yes Save PC and CCR Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance ...
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Section 5 Interrupt Controller If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. When the interrupt controller receives one or more interrupt requests, it selects ...
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Figure 5.5 shows the transitions among the above states. a. All interrupts are unmasked I 0 Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when interrupt ...
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Section 5 Interrupt Controller Priority level 1? No IRQ 0 Yes IRQ Figure 5.6 Process Up to Interrupt Acceptance when Rev. 4.00 Jan 26, 2006 page 114 of 938 REJ09B0276-0400 Program execution state Interrupt ...
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Interrupt Sequence Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Sequence Rev. 4.00 Jan 26, ...
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Section 5 Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time No. Item ...
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Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed interrupt ...
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Section 5 Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing ...
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Section 6 Bus Controller 6.1 Overview The H8/3067 Group has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
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Section 6 Bus Controller Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted when an external read cycle is immediately followed by an external ...
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Block Diagram Figure 6.1 shows a block diagram of the bus controller. Area Internal address bus decoder WAIT Internal signals CPU bus request signal DMAC bus request signal DRAM interface bus request signal CPU bus acknowledge signal DMAC bus ...
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Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Chip select Address strobe RD Read HWR High ...
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Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Bus Controller Registers Address * 1 Name H'EE020 Bus width control register H'EE021 Access state control register H'EE022 Wait control register H H'EE023 Wait control register L H'EE013 ...
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Section 6 Bus Controller 6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. Bit 7 ABW7 Modes Initial value and ...
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Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states Bit AST7 AST6 Initial value 1 1 Read/Write R/W R/W ASTCR is initialized ...
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Section 6 Bus Controller WCRH and WCRL are initialized to H' reset and in hardware standby mode. They are not initialized in software standby mode. WCRH 7 6 Bit W71 W70 Initial value 1 1 Read/Write R/W R/W ...
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Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit ...
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Section 6 Bus Controller WCRL 7 6 Bit W31 W30 Initial value 1 1 Read/Write R/W R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area ...
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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit ...
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Section 6 Bus Controller 6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A enables or disables release of the bus to an external device. Bit 7 6 A23E A22E ...
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Bit 6—Address 22 Enable (A22E): Enables this bit enables A output from PA 22 modified and PA has its ordinary port functions. 5 Bit 6 A22E Description the ...
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Section 6 Bus Controller 6.2.5 Bus Control Register (BCR Bit ICIS1 ICIS0 Initial value 1 1 Read/Write R/W R/W BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the area division unit, and ...
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Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst access cycle comprises 2 states 1 Burst access cycle comprises 3 states Bit 3—Burst Cycle Select ...
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Section 6 Bus Controller 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals output of a chip select signal is enabled ...
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Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1. 6.2.7 DRAM Control Register A (DRCRA Bit DRAS2 DRAS1 Initial value 0 0 Read/Write R/W R/W DRCRA is an 8-bit readable/writable register that ...
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Section 6 Bus Controller When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Bit 4—Reserved: This bit cannot be modified and is always read as ...
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Bit 0—Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If areas are not designated as DRAM space, this bit should not be set to 1. Bit 0 RFSHE Description RFSH pin refresh signal ...
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Section 6 Bus Controller Bits 7 and 6—Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row address/column address multiplexing method used on the DRAM interface. In burst operation, the row address used for comparison is determined by ...
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Bit 4—Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle insertion. When none of areas has been designated as DRAM space, refresh cycles are not inserted regardless of the setting of this bit. Bit 4 RCYCE ...
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Section 6 Bus Controller 6.2.9 Refresh Timer Control/Status Register (RTMCSR Bit CMF CMIE Initial value 0 0 Read/Write R(W)* R/W RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When the refresh timer is ...
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Bits 5 to 3—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 clocks obtained by dividing the system clock ( ). When the input clock is selected with bits ...
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Section 6 Bus Controller 6.2.11 Refresh Time Constant Register (RTCOR Bit Initial value 1 1 Read/Write R/W R/W RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is cleared. RTCOR and RTCNT are constantly ...
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Address Control Register (ADRCR) (Provided Only in Flash Memory R Version and Mask ROM Versions) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. Bit ...
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Section 6 Bus Controller 6.3 Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1- Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure ...
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CS Chip select signals (CS 0 are selected in ABWCR, ASTCR, WCRH, and WCRL. In 16-Mbyte mode, the area division units can be selected with the RDEA bit in BCR. ) can be output for areas ...
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Section 6 Bus Controller H'000000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'FEE000 On-chip registers (1) H'FEE0FF H'FEE100 H'FF7FFF H'FF8000 H'FF8FFF H'FF9000 H'FFEF1F H'FFEF20 H'FFFEFF H'FFFF00 H'FFFF1F H'FFFF20 On-chip registers (2) H'FFFFE9 H'FFFFEA ...
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Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and registers ...
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Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH/WCRL ABWn ASTn Wn1 Wn0 0 0 — — — — ...
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CS in the input state. To output chip select signals set to 1. For details, see section 8, I/O Ports. Output Output ...
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Section 6 Bus Controller 6.3.5 Address Output Method The H8/3067 Group provides a choice of two address update methods: either the same method as in the previous H8/300H Series (address update mode 1 method in which address update ...
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ADRCR is allocated to address H'FEE01E. In the flash memory version, the corresponding address is empty space, but it is necessary to confirm that no accesses are made to H'FEE01E in the program. When address update mode 2 is selected, ...
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Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data ...
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In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd ...
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Section 6 Bus Controller Table 6.4 Data Buses Used and Valid Strobes Access Area Size Read/Write 8-bit Byte Read access Write area 16-bit Byte Read access area Write Word Read Write Notes: 1. Undetermined data means that unpredictable data is ...
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Areas external expansion mode, areas are entirely external space. When area external space is accessed, signals CS Basic bus interface or DRAM interface can be selected for areas 2 to ...
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Section 6 Bus Controller 6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper ) is used in accesses to these areas. The LWR pin ...
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Two-State-Access Areas Figure 6.10 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper ) is used in accesses to these areas. The LWR pin is always high. Wait states data bus ( ...
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Section 6 Bus Controller 16-Bit, Three-State-Access Areas Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D bus ( accesses to odd ...
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Address bus Read access HWR LWR Write access Note Figure 6.12 ...
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Section 6 Bus Controller Address bus Read access HWR LWR Write access Note Figure 6.13 ...
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Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D even addresses and the lower data bus (D be inserted. Address bus Read ...
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Section 6 Bus Controller Address bus Read access Write access Note Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) Rev. 4.00 Jan 26, 2006 page 162 of 938 REJ09B0276-0400 Bus cycle T ...
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Address bus Read access Write access Note Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) 6.4.6 Wait Control When accessing external space, the H8/3067 Group can extend the bus cycle by inserting ...
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Section 6 Bus Controller Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the ...
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DRAM Interface 6.5.1 Overview The H8/3067 Group is provided with a DRAM interface with functions for DRAM control signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of DRAM. In the expanded modes, external address ...
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Section 6 Bus Controller Table 6.5 Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space (RAS Output Pin) DRAS2 DRAS1 DRAS0 Area Normal space 1 Normal space 1 0 Normal space 1 Normal space 1 ...
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Address Multiplexing When DRAM space is accessed, the row address and column address are multiplexed. The address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number of bits in the DRAM column address. ...
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Section 6 Bus Controller 6.5.5 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7 DRAM Interface Pins With DRAM Pin Designated Name UCAS PB4 Upper column address strobe LCAS PB5 ...
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If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is inserted unconditionally immediately ...
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Section 6 Bus Controller 6.5.7 Precharge State Control In the H8/3067 Group, provision is made for the DRAM RAS precharge time by always inserting one RAS precharge state (T ) when DRAM space is accessed. This can be changed to ...
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Wait Control In a DRAM access cycle, wait states can be inserted (1) between the T between the T state and T state Insertion of T Wait State between setting the RCW bit to ...
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Section 6 Bus Controller A 23 CSn(RAS) PB /PB 4 (UCAS /LCAS) Read access RD(WE /PB 4 (UCAS /LCAS) Write access RD(WE Note Figure 6.20 Example of Wait State Insertion ...
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When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0, PB5 can be used as an input/output ...
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Section 6 Bus Controller 6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used ...
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CSn(RAS (UCAS /LCAS) Read access RD(WE / (UCAS/LCAS) Write access RD(WE Note ...
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Section 6 Bus Controller Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and Row Address Compared in Burst Access DRCRB Operating Mode MXC1 Modes 1 and 2 0 (1-Mbyte) 1 Modes 3, 4, and 5 0 ...