HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 110

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 4 Exception Handling
4.3
Interrupt exception handling can be requested by seven external sources (NMI, IRQ
36 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),
DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication
interface (SCI), and A/D converter. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted*. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
Note: * In the flash memory and flash memory R versions, NMI input is sometimes disabled. For
For details on interrupts see section 5, Interrupt Controller.
Rev. 4.00 Jan 26, 2006 page 86 of 938
REJ09B0276-0400
Notes: Numbers in parentheses are the number of interrupt sources.
details see 18.6.4, NMI Input Disable Conditions.
1.
2.
Interrupts
Interrupts
When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
When the DRAM interface is used as an interval timer, it generates an interrupt request
at compare match.
Figure 4.5 Interrupt Sources and Number of Interrupts
External interrupts
Internal interrupts
NMI (1)
IRQ to IRQ (6)
WDT*
DRAM interface*
16-bit timer (9)
8-bit timer (8)
DMAC (4)
SCI (12)
A/D converter (1)
0
1
(1)
5
2
(1)
0
to IRQ
5
), and