HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 243

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3
DTIE
0
1
Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer
activation source. Some of the selectable sources differ between channels A and B.
Bit 2
DTS2
0
1
Note: See section 7.3.4, Data Transfer Control Registers (DTCR).
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 7.4.9, Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
Bit 1
DTS1
0
1
0
1
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
Bit 0
DTS0
0
1
0
1
0
1
0
1
Description
Compare match/input capture A interrupt from 16-bit timer
channel 0
Compare match/input capture A interrupt from 16-bit timer channel 1
Compare match/input capture A interrupt from 16-bit timer channel 2
Conversion-end interrupt from A/D converter
Transmit-data-empty interrupt from SCI channel 0
Receive-data-full interrupt from SCI channel 0
Falling edge of DREQ input (channel B)
Transfer in full address mode (channel A)
Low level of DREQ input (channel B)
Transfer in full address mode (channel A)
Rev. 4.00 Jan 26, 2006 page 219 of 938
Section 7 DMA Controller
REJ09B0276-0400
(Initial value)
(Initial value)