HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 250

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 DMA Controller
DTCRB
DTCRB is initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit
enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is
enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the
CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further
information on operation in block transfer mode, see section 7.6.6, NMI Interrupts and Block
Transfer Mode.
DTME is set to 1 by reading the register while DTME = 0, then writing 1.
Bit 7
DTME
0
1
Bit 6—Reserved: Although reserved, this bit can be written and read.
Rev. 4.00 Jan 26, 2006 page 226 of 938
REJ09B0276-0400
Bit
Initial value
Read/Write
Data transfer master enable
Enables or disables data
transfer, together with
the DTE bit, and is cleared
to 0 by an interrupt
Description
Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt
occurs)
Data transfer is enabled
DTME
R/W
7
0
Reserved bit
R/W
Ñ
6
0
Destination address
increment/decrement
Destination address
increment/decrement enable
These bits select whether
the destination address
register (MARB) is incremented,
decremented, or held fixed
during the data transfer
DAID
R/W
5
0
DAIDE
R/W
Transfer mode select
Selects whether the
block area is the source
or destination in block
transfer mode
4
0
TMS
R/W
3
0
DTS2B
R/W
2
0
Data transfer select
2B to 0B
These bits select the data
transfer activation source
DTS1B
R/W
1
0
(Initial value)
DTS0B
R/W
0
0